Interrupt Priority Table - Texas Instruments UCD3138 Technical Reference Manual

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Name
BRN_OUT_INT Brownout
EXT_INT External Interrupts
WDRST_INT Watchdog Control
WDWAKE_INT Watchdog Control
SCI_ERR_INT UART or SCI Control
SCI_RX_0_INT UART or SCI Control
SCI_TX_0_INT UART or SCI Control
SCI_RX_1_INT UART or SCI Control
SCI_TX_1_INT UART or SCI Control
PMBUS_INT
DIG_COMP_INT 12-bit ADC Control
FE0_INT Front End 0
FE1_INT Front End 1
FE2_INT Front End 2
PWM3_INT 16-bit Timer PWM 3
PWM2_INT 16-bit Timer PWM 2
PWM1_INT 16-bit Timer PWM 1
PWM0_INT 16-bit timer PWM 0
OVF24_INT 24-bit Timer Control
CAPTURE_1_INT 24-bit Timer Control
COMP_1_INT 24-bit Timer Control
CAPTURE_0_INT 24-bit Timer Control
COMP_0_INT 24-bit Timer Control
Constant power/current
CPCC_INT
module
ADC_CONV_INT 12-bit ADC Control
FAULT_INT Fault Mux Interrupt
DPWM3 DPWM3
DPWM2 DPWM2
DPWM1 DPWM1
DPWM0 DPWM0
EXT_FAULT_INT External Faults
SYS_SSI_INT System Software
SNIU028A – February 2016 – Revised April 2016
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Table 16-2. Interrupt Priority Table
Module Component
or Register
Brownout interrupt
Interrupt on one external input pins for faults inputs
Interrupt from watchdog exceeded (reset)
Wakeup interrupt when watchdog equals half of set watch
time
UART or SCI error Interrupt. Frame, parity or Overrun
UART0 RX buffer has a byte
UART0 TX buffer empty
UART1 RX buffer has a byte
UART1 TX buffer empty
PMBus related interrupt
Digital comparator interrupt
"Prebias complete", "Ramp Delay Complete", "Ramp
Complete", "Load Step Detected" , "Over-Voltage Detected",
"EADC saturated"
"Prebias complete", "Ramp Delay Complete", "Ramp
Complete", "Load Step Detected" , "Over-Voltage Detected"
"EADC saturated"
"Prebias complete", "Ramp Delay Complete", "Ramp
Complete", "Load Step Detected" , "Over-Voltage Detected",
"EADC saturated"
16-bit Timer PWM3 counter overflow or Compare interrupt
16-bit Timer PWM2 counter Overflow or Compare interrupt
16-bit Timer PWM1 counter overflow or Compare interrupt
16-bit Timer PWM1 counter overflow or Compare interrupt
24-bit Timer counter overflow interrupt
24-bit Timer Capture 1 interrupt
24-bit Timer Compare 1 interrupt
24-bit Timer Capture 0 interrupt
24-bit Timer Compare 0 interrupt
Mode switched in CPCC module Flag needs to be read for
details
ADC end of conversion interrupt
Analog Comparator Interrupts, Over-Voltage Detection,
Under-Voltage Detection, LLM Load Step Detection
Same as DPWM1
same as DPWM1
1. Every (1-16) switching cycles
2. CLF flag shutdown
3. Mode switching
4. IDE, DCM detection
same as DPWM1
Fault pin interrupt
System software interrupt
Copyright © 2016, Texas Instruments Incorporated
Central Interrupt Module (CIM)
Description
Control System Module
Priority
0 (Lowest)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 (highest)
503