2.17.7 Sample Trigger Enable Bits; 2.18 Period And Event Registers; 2.19 Phase Trigger Registers; 2.20 Cycle Adjust Registers - Texas Instruments UCD3138 Technical Reference Manual

DPWM Control Register 2
Note that using adaptive offset will cause the phase delay of the control loop to change somewhat as the
duty cycle changes.
The Fixed Offset in mode 3 is a value of 4. This is added to the DPWMADAPTIVE Register and to the
Event 1 and Duty Terms.

2.17.7 Sample Trigger Enable Bits

Sample Trigger 2 is only driven by the Sample Trigger 2 Register - DPWMSAMPTRIG2. Setting the
SAMPLE_TRIG_2_EN bit enables it.
SAMPLE_TRIG_1_EN enables Sample Trigger 1.

2.18 Period and Event Registers

The period and event registers DPWMPRD, DPWMEV1, DPWMEV2, DPWMEV3, and DPWMEV4 have
different effects in different modes. See DPWM Modes below for more information about each mode.
Generally the registers work somewhat as described above in
controlled by the filter, and the differences between Event Registers are used as dead times.

2.19 Phase Trigger Registers

The DPWMPHASETRIG register is a low resolution (4 ns.) register. It dictates the number of 4 ns. steps
between the start of the period and the output of a sync pulse for synchronizing a slave DPWM. See
Section 2.4.

2.20 Cycle Adjust Registers

DPWMCYCADJA and DPWMCYCADJB are registers that are added to the Filter Duty before the DPWM
pulse width is calculated. They have different effects in different modes, see the DPWM Mode sections
above. They are signed high resolution registers so that the duty can be increased or decreased from the
Filter value. They only have 16 bits, so they cannot adjust the full 18 bit range of the DPWM. But their
range is still +-8 milliseconds, which is typically more than a whole switching period
High resolution is 250 picosec, and the range of a signed 16 bit value is ±2
15
2 x 250 psec = 8.192 msec

2.21 Resonant Duty Register

This register is used in LLC topologies to produce the correct Filter Duty output. The Filter output is
multiplied by this register to calculate Filter Duty. In the LLC reference firmware (UCD3138LLCEVM-028) it
is set to 1/2 of the maximum desired period. In this case, bits 13-0 are used as an unsigned number. To
enable this mode, the DPWM must be in Resonant Mode, and the FILTER_DUTY_SEL field in
DPWMCTRL2 must be set to a 2.
If FILTER_DUTY_SEL is set to 0 or 1 and the DPWM is in resonant mode, the 16 bit signed contents of
the register are added to the Filter Period value, and the result is used for the DPWM Period. This is
another option for adjusting the resonant mode timing to match other modes across a mode shift. This
mode is not currently used in any topologies.

2.22 DPWM Fault Control Register

See Chapter 6 for information on the DPWMFLTCTRL register.

2.23 DPWM Overflow Register

The DPWMOVERFLOW register has, as already mentioned, 2 bits which give the input status of the
DPWM pins when they are used as general purpose I/O.
It also has 6 bits which indicate that the protection logic for the DPWM has detected overflows.
64
Digital Pulse Width Modulator (DPWM)
Copyright © 2016, Texas Instruments Incorporated
Section 2.2. Often, the pulse widths are
15
. So
SNIU028A – February 2016 – Revised April 2016
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