Output Multiplier Select - Texas Instruments UCD3138 Technical Reference Manual

Filter Control Register

4.3.8 Output Multiplier Select

The OUTPUT_MULT_SEL bits select what value is multiplied by the filter output to determine the DPWM
pulse width. See the
1. KComp - This enables special scaling of the output to the DPWM independent of the period.
2. Switching Period – This results in the Filter output translating directly to a DPWM on-time percentage.
Full scale on the filter output will equal a 100 % on time.
3. Feed Forward value – This permits the output of the filter to be controlled by the output of another
filter. This could be, for example, a voltage feed-forward value
4. Resonant Duty value received from the DPWM module - This is used for resonant mode, for example
for LLC architecture.
Note that the default is KComp. This is not intuitive, especially for users of the UCD3000 series digital
power controller. They UCD3000 had no options in this area, period was always used. It is easy to
overlook this bitfield when setting up for a simple period based system. The OUTPUT_MULT_SEL register
works with the FILTERMUX register in the Loop Mux for value selections. FILTERMUX selects which
KComp is used, which DPWM Period is used, and which Filter output is used for Feed Forward. Resonant
Duty also comes from a DPWM module and is also selected by FILTERMUX. See 5.4 Filter Mux Register
(FILTERMUX).
Switching Period is provided by the DPWM. The default is the value from the DPWM Period register, and
this is used for most topologies. However, there are two other DPWM registers which can also be sent to
the Filter for this value. See 2.17.3 Filter Duty Select, for more details.
4.3.9 Switching Period as Output Multiplier
Using the Switching Period as an output multiplier leads to the DPWM duty being directly proportional to
the Filter output, with a full range output being equal to about 100% of the period. Here is the bit pattern of
the multiply:
The filter output is a 24 bit signed number, with a range from 0x7fffff (8388607) to 0x800000 (-8388608).
All of the output multipliers are unsigned 14 bit numbers with a range from 0x3fff (16383) to 0.
The product of these two numbers is a 38 bit number. This number is then scaled and rounded down to a
18 bit number and used for the high resolution events in the DPWM.
So suppose that the filter output is at about 50% or 4194304. If the period is the same as the example
above, 2500, the product of the two will be 10485760000. To reduce this from a 38 bit signed number to a
18 bit unsigned number, we drop the sign bit off the top and divide by 2
sense in terms of DPWM timing, so they will be clamped to zero.
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Dividing by 2 gives a result of 20000. This is a high resolution value for the 4 GHz clock of the DPWM.
To convert it to the lower resolution, 250 MHz clock used for the period, we need to divide by 16. This
gives a result of 1250, or half the period. Other filter output values follow the exact same scaling.
There is a register in the Loop Mux, the FILTERMUX register, which selects the period source for each
filter.
See Section 5.14 for more information on this register. Here is an example of its use:
LoopMuxRegs.FILTERMUX.bit.FILTER0_PER_SEL = 2; //use DPWM2 period for filter 0
150
Filter
Filter Reference section for specific bit assignments. The options are:
Copyright © 2016, Texas Instruments Incorporated
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. Negative filter outputs make no
SNIU028A – February 2016 – Revised April 2016
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