Comparator Ramp Control 0 Register (Compramp0); Comparator Ramp Control 0 Register (Compramp0) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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6.11.8 Comparator Ramp Control 0 Register (COMPRAMP0)

Comparator Ramp Control 0 Register (COMPRAMP0)
31
START_VALUE_SEL
R/W-0000
23
15
7
CLKS_PER_STEP
R/W-0 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-8. Comparator Ramp Control 0 Register (COMPRAMP0) Register Field Descriptions
Bit Field
31-28 START_VALUE
_SEL
27-10 STEP_SIZE
9-5 CLKS_PER_STEP R/W
4 DPWM3_TRIG
_EN
3 DPWM2_TRIG
_EN
2 DPWM1_TRIG
_EN
SNIU028A – February 2016 – Revised April 2016
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Figure 6-12. Comparator Ramp Control 0 Register (COMPRAMP0)
28
R/W-00 0000 0000 0000 0000
STEP_SIZE
R/W-00 0000 0000 0000 0000
5 4
DPWM3_TRIG
_EN
R/W-0
Type Reset
R/W 0000
Configures comparator ramp starting value
0 = Filter 0 Output (Bits 17-11) (Default)
1 = Filter 1 Output (Bits 17-11)
2 = Filter 2 Output (Bits 17-11)
3 = Analog Comparator Threshold A Value
4 = Analog Comparator Threshold B Value
5 = Analog Comparator Threshold C Value
6 = Analog Comparator Threshold D Value
7 = Analog Comparator Threshold E Value
8 = Analog Comparator Threshold F Value
9 = Analog Comparator Threshold G Value
R/W 00 0000
Programmable 18-bit unsigned comparator step with Bits 27:24 representing the
0000
integer portion of the comparator step (0-15 Comparator steps of 19.5mV each) and
0000
Bits 23:10 representing the fractional portion of the comparator step
0000
0 0000
Selects number of MCLK (HFO_OSC/8) clock cycles per comparator step where
number of subcycles can vary from 1 to 32
0 = 1 MCLK clock cycles per step (Default)
1 = 2 MCLK clock cycles per step
2 = 3 MCLK clock cycles per step
.......
31 = 32 MCLK clock cycles per step
R/W 0
Enables DPWM Trigger from DPWM 3 to Analog Comparator Ramp 0
0 = DPWM 3 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 3 trigger routed to Analog Comparator Ramp 0
R/W 0
Enables DPWM Trigger from DPWM 2 to Analog Comparator Ramp 0
0 = DPWM 2 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 2 trigger routed to Analog Comparator Ramp 0
R/W 0
Enables DPWM Trigger from DPWM 1 to Analog Comparator Ramp 0
0 = DPWM 1 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 1 trigger routed to Analog Comparator Ramp 0
Copyright © 2016, Texas Instruments Incorporated
27
R/W-00 0000 0000 0000 0000
STEP_SIZE
3
DPWM2_TRIG DPWM1_TRIG
_EN _EN
R/W-0 R/W-0
Description
Fault Mux Registers Reference
STEP_SIZE
10 9
CLKS_PER_STEP
R/W-0 0000
2 1
DPWM0_TRIG RAMP_EN
_EN
R/W-0
Fault Mux
24
16
8
0
R/W-0
247