Filter Enable - Texas Instruments UCD3138 Technical Reference Manual

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4.3.1 Filter Enable

The Filter Enable (FILTER_EN) bit enables the filter. Unlike the DPWM and Front End, there are no filter
enable bits in the GLBEN (Global Enable) Register in the Loop Mux registers. These bits are unnecessary
for the filter because it only operates when it is triggered by the Front End or some other external event.
The default for the Filter Enable bit is a 1, which enables the filter. If the filter is disabled after running for
at least one cycle, the value sent to the DPWM will continue to control the DPWM. In addition, the last
Filter Status state will also remain.
4.3.2 Use CPU Sample
The CPU Sample bit (USE_CPU_SAMPLE) is used for open loop testing of the Filter and DPWM
configuration, or in other cases where a firmware input to the Filter is desired. If the USE_CPU_SAMPLE
bit is set, the Filter input comes from the CPU_SAMPLE bit field in the CPU Xn register (CPUXN).
Here is an example of using CPU_SAMPLE:
Filter1Regs.FILTERCTRL.bit.USE_CPU_SAMPLE = 1; //enable CPU sample
Filter1Regs.CPUXN.bit.CPU_SAMPLE = -34; //put negative value into CPU sample
4.3.3 Force Start
The FORCE_START bit triggers a single filter calculation. It can be used with the CPU_SAMPLE value to
run a controlled calculation in the filter. If CPU Sample is not enabled, it will use whatever input is selected
for this filter.
4.3.4 Kp Off, Kd Off, Ki Off
The KP_OFF, KD_OFF, and KI_OFF bits disable these sections of the filter, and replace those values with
a zero. They also clear any history to a zero where it is present (I and D). Note that the history values are
loaded with a zero the next time the filter is triggered. Normally the EADC is triggered by a sample trigger
signal from a DPWM module. When the EADC conversion is complete, the filter is triggered. The filter can
also be triggered by writing a 1 to the FORCE_START bit in the FILTERCTRL register. If neither of these
events happens, the history will not be reset. So if the DPWM is not running, the history will not be
cleared. Even if the DPWM is running, writing a 1 followed by a 0 to the KD and KI_OFF bits will not
always clear the history. It depends if the filter is triggered and run while the bits are 1. If a quick clear is
desired, use the FILTERPRESET register instead.
4.3.5 Kd Stall, Ki Stall
The KD_STALL and KI_STALL registers stall these filter elements at their current value. They do not reset
them. They are useful for suppressing response to transients when such response is not desirable.
4.3.6 Nonlinear Mode
The NL_MODE bit selects which nonlinear mode is used. 0 is for asymmetric mode, while 1 selects
symmetric mode. Refer to
4.3.7 Output Scaling
The 3 OUTPUT_SCALE bits permit shifting of the filter output. This gives flexibility in the scaling of the
filter peripherals. It is a 2's complement number, where 0 means no shift, 1 means a shift right by 1, 2
means shift right by 2, -1 means shift left by 1, and so on.
Filter1Regs.FILTERCTRL.bit.OUTPUT_SCALE = -3; //shift filter output left by 3
SNIU028A – February 2016 – Revised April 2016
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Section 4.5 through Section 4.8
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