Error Adc And Front End Gain; Front End Gain; Eadc Error Output - Texas Instruments UCD3138 Technical Reference Manual

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3.1

Error ADC and Front End Gain

The Error ADC (EADC) is a high speed 6 bit ADC converter.

3.1.1 Front End Gain

The Front End gain (the gain before the EADC) can be adjusted to 1X, 2X, 4X, and 8X. This gives an
EADC resolution of 8mV, 4mV, 2mV, and 1mV respectively.
To set a fixed front end gain, the gain value is written to the AFE_GAIN bits in the EADC Control register.
FeCtrl0Regs.EADCCTRL.bit.AFE_GAIN = 2; //set AFE gain to 4X
In addition, there are 2 automatic gain setting modes, available only on Front End 0. They are enabled by
setting the AUTO_GAIN_SHIFT_ENABLE bit in the EADC control register.
FeCtrl0Regs.EADCCTRL.bit.AUTO_GAIN_SHIFT_EN = 1; //enable auto gain shift mode.
In the simpler mode, the gain is shifted to the next lower mode whenever the EADC over or underflows.
The gain is increased if the EADC output is less than +-1/4 of its range at the current gain.
By setting the AUTO_GAIN_SHIFT_MODE bit in the EADCCTRL register, the second auto gain mode can
be enabled. In this mode, the shift points are set by the Filter nonlinear mode thresholds. These
thresholds are described in
register in Chapter 5

3.1.2 EADC Error Output

The internal EADC output is a 6 bit two's complement number. Depending on AFE gain, the least
significant EADC bit can have a value of 1 to 8 mV. To simplify automatic AFE gain changes, this EADC
output is shifted depending on the AFE gain, giving a 9 bit output to the filter.
This way, regardless of the AFE gain, the least significant bit will always have a resolution of 1mV.
Depending on AFE gain, the bits and range of the output actually used will change:
Analog Gain
1
2
4
8
SNIU028A – February 2016 – Revised April 2016
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Section 4.5. There are 3 Filters with non linear thresholds. The FECTRLxMUX
selects which set of nonlinear thresholds are used with each Front End.
AFE_GAIN Bits Input Range (mV)
0 +248 to -256
1 +124 to -128
2 +62 to -64
3 +31 to -32
Copyright © 2016, Texas Instruments Incorporated
Table 3-1.
Bits Used
3 - 8
2 - 7
1 - 6
0 - 5

Error ADC and Front End Gain

Measurement
Left Shift
Resolution (mV)
3 8
2 4
1 2
0 1
Front End
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