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The compare action is programmable for each compare block to one of 4 states:
00 = No action (Default)
01 = Set pin
10 = Clear pin
11 = Toggle pin
To set Compare 0 up to toggle the pin:
TimerRegs.T16PWM0CMPCTRL.bit.PWM_OUT_ACTION0 = 3;
There is also an OUT bit and an OUT_DRV bit. When a 1 is written to the OUT_DRV bit, the OUT bit
value is placed on the pin. Both compare blocks and the OUT bit can work seamlessly together.
All of this only works, of course, if the OUT_ENA bit is set as well. The default state for the pin is as an
input, so it is necessary to set the OUT_ENA bit if output is desired.
As already mentioned, each compare block can cause an interrupt, if it is enabled. The interrupt enable
and flag bits are described in
11.10 T16 Shadow Bit
The compare control register also contains a SHADOW bit. It is normally cleared, but it can be set this
way:
TimerRegs.T16PWM0CMPCTRL.bit.SHADOW = 1;
The SHADOW bit is useful for a PWM output that will vary over time. The compare blocks work by
detecting when the compare data is equal to the 16 bit counter value. This works fine if the compare data
is never changed.
If, however, the compare data value is reduced at the wrong time, it is possible for the compare block to
miss it, and therefore for the PWM pulse to remain on for the entire period.
For example, suppose that the compare 1 data value is 100. Suppose that the counter value is 90, and
the compare 1 data register is written to, changing the data value to 80. In this case, for one cycle, the
compare 1 event will not occur. Normally for PWM, compare 1 is used to turn off the PWM pulse. So the
result will be a PWM pulse that is on for the entire period.
If the SHADOW bit is set, it enables buffer registers, called shadow registers, for the compare data
registers. The data written is stored in the shadow register until the next compare event, and only then is it
written into the compare data register.
So to return to the example, the 80 will not be written into the data register until after the counter reaches
100, so the pulse will stop at 100, instead of going on to the end.
There are two side effects to using the shadow register:
1. Read always reads from the actual data register. So if the data register is written to and then read from
before the next compare event for that block, the old data will still be read.
2. If the value written to the data register is higher than the current value, it may be possible to have two
compare events. For example if the counter value is 70, the data value is 80, and the new data value
is 100, the compare event will occur at 80, and the shadow register will be copied into the data
register. Then a second compare event will occur when the 16 bit counter reaches 100. This should
not be a problem if the compare action is a set or reset, but if the action is a toggle, this could be a
problem. Or if the compare interrupt is being used.
Of course, the same thing could happen without the shadow bit set.
11.11 T16 Interrupts
The T16 module generates 3 interrupts. All of them are combined into a single signal for the CIM.
Therefore, if more than one interrupt is enabled for a module, it will be necessary to read the module
registers in order to determine the source(s) of the interrupt. It will also be necessary to write to all the
interrupt flags which are set to clear the interrupt.
SNIU028A – February 2016 – Revised April 2016
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Section 11.21
for details.
Copyright © 2016, Texas Instruments Incorporated
T16 Shadow Bit
401
Timer Module Overview
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