Dpwm Control Register 1 (Dpwmctrl1) - Texas Instruments UCD3138 Technical Reference Manual

DPWM 0-3 Registers Reference
Table 2-7. DPWM Control Register 1 (DPWMCTRL1) Register Field Descriptions (continued)
Bit Field
7 PWM_HR_MULTI
_OUT_EN
6 SFRAME_EN
5 PWM_B_PROT
_DIS
4 PWM_A_PROT
_DIS
3-2 HIRES_SCALE
1 ALL_PHASE_CLK
_ENA
0 HIRES_DIS
72
Digital Pulse Width Modulator (DPWM)
Type Reset
R/W 0
Control bit for Hi-Res Block
0 = Disabled (Default)
1 = Enabled
R/W 0
PWM Single Step Frame Mode Enable
0 = Disable Single Frame Mode (Default)
1 = Enable Single Step Frame Mode. One EADC sample is requested, CLA then
Filters, then one PWM duty cycle performed, then wait on Single Frame Trigger
toggle before advancing to next frame.
R/W 0
PWM B Asynchronous Protection Disable
0 = Allows asynchronous protection to turn off PWM B Output (Default)
1 = Disables asynchronous protection from turning off PWM B Output
R/W 0
PWM A Asynchronous Protection Disable
0 = Allows asynchronous protection to turn off PWM A Output (Default)
1 = Disables asynchronous protection from turning off PWM A Output
R/W 00
Determines resolution of high resolution steps
00 = Resolution of 16 phases. Full resolution enabled. Resolution step = PCLK/16
(Default)
11 = Resolution of 2 phases. Resolution step = PCLK/2
10 = Resolution of 4 phases. Resolution step = PCLK/4
01 = Resolution of 8 phases. Resolution step = PCLK/8
00 = Resolution of 16 phases. Full Resolution enabled.
Resolution step = PCLK/16
R/W 1
High Speed Oscillator Phase Enable
0 = Enables only required phases of clock when needed
1 = Enables all phases of high resolution clock from oscillator (Default)
R/W 0
PWM High Resolution Disable
0 = Enable High Resolution logic (Default)
1 = Disable High Resolution logic
Copyright © 2016, Texas Instruments Incorporated
Description
SNIU028A – February 2016 – Revised April 2016
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