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1
S
EOM
PEC_VALID
DATA_RDY
RD_BYTE_COUNT
Write to ACK
1. RXBUF is full, number of bytes received is equivalent to RX_BYTE_ACK_CNT. DATA_RDY is set and
RD_BYTE_COUNT is loaded with a 4. The interface is prepared to stretch the clock. This occurs t
after the falling edge of the clock for bit 8.
2. The firmware reads the data from RXBUF and writes a 1 to the ACK bit. This turns off the clock
stretch. The delay between write to ACK and disable of clock stretch is t
clears the DATA_RDY bit and the RD_BYTE_COUNT bits.
3. On the falling edge of PMBUS_CLK indicating the STOP signal, the EOM bit is set, and the
PEC_VALID bit is set or cleared to indicate if the last byte was a valid PEC. The timing after the falling
edge is tEOM.
If step 3 is delayed, clock stretching of the next valid address will occur in the same way as described in
Section
10.3.1.
The exact same sequence will occur if the 3rd data byte is replaced with a valid PEC, except that the
PEC_VALID bit will be always set.
For messages with 5 through 7 bytes, the sequence will be as described below:
1
S
EOM
PEC_VALID
DATA_RDY
RD_BYTE_COUNT
Write to ACK
There are 4 items here:
1. DATA_RDY and RD_BYTE_COUNT set as described above
2. DATA_RDY and RD_BYTE_COUNT cleared by read from PMBST, data read from RXBUF, 1 written
to ACK bit. Clock stretch released.
SNIU028A – February 2016 – Revised April 2016
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7
1
1
8
Address Wr A
Command
Figure 10-6. Timing Diagram
7
1
1
8
Address Wr A
Cmd
Figure 10-7. Write 4 Bytes + Command
Copyright © 2016, Texas Instruments Incorporated
PMBus Slave Mode Command Examples
8
1
1
8
A Data Byte
A
Data Byte
8
1
1
8
1
A
Byte
A
Byte
A
1
8
1
1
A
A
P
Data Byte
1
3
2
. Reading from PMBST
ACKWRITE
8
1
8
1
1
A
A
P
Byte
Byte
3
1
4
2
PMBus Interface/I2C Interface
DRDY
359
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