System Exception Status Register (Sysesr); System Exception Status Register (Sysesr) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

www.ti.com

16.5.3 System Exception Status Register (SYSESR)

Address FFFFFFE4
The System Exception Status Register contains flags for different reset/abort sources. On power-up, all
bits are cleared to 0. When a reset condition is recognized, the appropriate bit in the Register is set and
the value of the bit is maintained through the reset. When a new reset condition occurs, the current
contents of this Register are not cleared. The contents of this Register are cleared on a power-on reset or
by software.
15 14
PORRST CLKRST
R/W-0 R/W-0
7 6
SWRST
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-6. System Exception Status Register (SYSESR) Register Field Descriptions
Bit Field
15 PORRST
14 CLKRST
13 WDRST
12 ILLMODE
SNIU028A – February 2016 – Revised April 2016
Submit Documentation Feedback
Figure 16-6. System Exception Status Register (SYSESR)
13 12
WDRST ILLMODE
R/W-0 R/W-0
Type Reset
R/W 0
Power-On reset flag. Set when power-on reset is asserted. Reset is asserted as long
as power-on-reset is active. Whenever a device is powered, this bit is set.
User and privilege modes (read
0 = Power-up reset has not occurred since the last clear
1 = Power-up reset has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
R/W 0
This bit represents the clock fail flag. This bit indicates a clock fault condition has
occurred. After power-on-reset, the CLKRST is reset to 0. Value remains unchanged
during other resets.
User and privilege modes (read)
0 = Clock failure has not occurred since the last clear
1 = Clock failure has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0 1 = No effect
R/W 0
This bit represents the watchdog reset flag. This bit indicates that the last reset was
caused by the watchdog.
User and privilege modes (read
0 = Watchdog reset has not occurred since the last clear
1 = Watchdog reset has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0 1 = No effect
R/W 0
This bit represents the illegal mode flag. This bit is set when the mode bits in the
program status Register are set to an illegal value.
User and privilege modes (read)
0 = Illegal mode has not occurred since the last clear
1 = Illegal mode has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Copyright © 2016, Texas Instruments Incorporated
SYS – System Module Registers Reference
11 10
ILLADR ILLACC
R/W-0 R/W-0
Reserved
R-000 0000
Description
9 8
PILLACC ILLMAP
R/W-0 R/W-0
0
511
Control System Module