T24 – 24 Bit Free-Running Timer With Capture And Compare - Texas Instruments UCD3138 Technical Reference Manual

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11.1 T24 – 24 Bit Free-Running Timer with Capture and Compare
Here is a block diagram of the T24 Module:
ICLK
FAULT0
TCAP
Note that the UCD3138A64 and UCD3138128 add a second capture module – CAP1. The pin names are
TCAP0 and TCAP1.
11.2 T24 Clock Source, Prescaler and Counter
The core of the T24 timer is a 24 bit free-running counter. The clock input for the T24 timer can come from
a clock within the UCD3138, ICLK, which is nominally 15.6 MHz. Consult the UCD3138 device datasheet
for the precise specification.
It can also be used with an external clock from the FAULT-0 pin.
The internal clock is the default. To select the external clock source instead, execute this C equation:
TimerRegs.T24CNTCTRL.bit.EXT_CLK_SEL = 1;
All C code references in this document use standard TI header files, provided as part of the UCD3138
EVM (UCD3138PFCEVM-026, UCD3138LLCEVM-028 etc) reference firmware.
• The first term, TimerRegs, refers to the Timer Register block
• The second term, T24CNTCTRL, refers to the specific register within that block
• Bit refers to the bit map. EXT_CLK_SEL refers to the specific bit field within the bit map
The clock then runs through a prescaler. The prescaler is controlled by an 8 bit register. Register values
from 0 to 255 correspond to dividing the clock by 1 to 256.
The divider count always equals register +1. The register C code is:
TimerRegs.T24CNTCTRL.bit.PRESCALE = 255;//Load with maximum divide ratio
With the nominal ICLK, and the 24 bit counter, a divide of 256 means that the timer will free run for about
4.5 minutes before overflowing.
Counter overflow can be used to generate an interrupt, if desired. The default is for the interrupt to be
disabled. To enable it, here is the C code:
TimerRegs.T24CNTCTRL.bit.OV_INT_ENA = 1;
There is also a bit that can be polled to indicate that an overflow has occurred:
result = TimerRegs.T24CNTCTRL.bit.OV_FLAG;
It is necessary to write a 1 to the OV_FLAG to clear it. This will also clear the overflow interrupt.
The 24 bit free running counter can be read by firmware to provide a time base. For example, to measure
the time required for a section of firmware, simply read the counter at the beginning and end of the section
and subtract the start count from the end count. To read from the counter:
result = TimerRegs.T24CNTDAT.bit.CNT_DAT;
SNIU028A – February 2016 – Revised April 2016
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Prescaler
Capture 0
24 Bit
Counter
CAP0
Interrupt
Figure 11-1.
Copyright © 2016, Texas Instruments Incorporated
T24 – 24 Bit Free-Running Timer with Capture and Compare
OVF24 Interrupt
Compare 0
Compare 1
CMP0 Interrupt
CMP1 Interrupt
397
Timer Module Overview