24-Bit Counter Control Register (T24Cntctrl) - Texas Instruments UCD3138 Technical Reference Manual

Timer Module Register Reference

11.21.2 24-bit Counter Control Register (T24CNTCTRL)

Address FFF7FD04
15
PRESCALE
R/W-0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-2. 24-bit Counter Control Register (T24CNTCTRL) Register Field Descriptions
Bit Field
15-8 PRESCALE
7-3 Reserved
2 EXT_CLK_SEL
1 OV_INT_ENA
0 OV_FLAG
406
Timer Module Overview
Figure 11-5. 24-bit Counter Control Register (T24CNTCTRL)
Type Reset
R/W 0000
Defines the prescaler value used to select the 24-bit counter resolution. The
0000
minimum divider ratio is 4, prescaler value less than 3 defaults to 3. Counter
Resolution = (Prescaler Value+1)*1/ICLK
R/W 00000
R/W 0
External Clock Select
0 = Selects ICLK as clock for 24-bit counter (Default)
1 = Selects External Clock on FAULT-0 as clock for 24-bit counter
R/W 0
Counter Overflow Interrupt Enable
0 = Disables 24-bit Counter Overflow Interrupt (Default)
1 = Enables 24-bit Counter Overflow Interrupt
R 0
Indicates a counter overflow. Overflow event is cleared by writing a '1' to this bit. If a
clear and an overflow event occur at the same time, the flag will remain high (set has
priority versus clear).
0 = No counter overflow since last clear
1 = Counter overflow since last clear
Copyright © 2016, Texas Instruments Incorporated
8 7
Reserved
R-00000
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
3 2 1 0
EXT_ OV_ OV_
CLK_ INT_ FLAG
SEL ENA
R/W-0 R/W-0 R-0
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