Eadc Control Register (Eadcctrl); Eadc Control Register (Eadcctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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3.7.9 EADC Control Register (EADCCTRL)

Address 0x0008_0020 – Front End Control 2 EADC Control Register
Address 0x000B_0020 – Front End Control 1 EADC Control Register
Address 0x000E_0020 – Front End Control 0 EADC Control Register
28
D2S_COMP_EN
R/W-0
23 22
SAMP_TRIG_SCALE
R/W-0000
15 14
EADC_INV AUTO_GAIN
_SHIFT_MODE
R/W-0 R/W-0
7 6
EADC_MODE
R/W-000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-11. EADC Control Register (EADCCTRL) Register Field Descriptions
Bit Field
28 D2S_COMP_EN
27 EN_HYST_HIGH
26 EN_HYST_LOW
25-22 SAMP_TRIG
_SCALE
21 FRAME_SYNC
_EN
20 SCFE_CNT_RST
19-16 SCFE_CNT_INIT
15 EADC_INV
SNIU028A – February 2016 – Revised April 2016
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Figure 3-17. EADC Control Register (EADCCTRL)
27
EN_HYST_HIGH EN_HYST_LOW
R/W-0
21 20
FRAME_SYNC SCFE_CNT
_EN _RST
R/W-0 R/W-0
13 12
AUTO_GAIN AVG_WEIGHT
_SHIFT_EN _EN
R/W-0 R/W-0
5 4
AFE_GAIN
R/W-11
Type Reset
R/W 0
Analog Front End Ramp Comparator Enable
0 = Analog Front End Ramp Comparator disabled (Default)
1 = Analog Front End Ramp Comparator enabled
R/W 0
Increase comparator trip point by ~70mV
0 = Disables increase of ramp comparator trip point (Default)
1 = Enables increase of ramp comparator trip point
R/W 0
Decrease comparator trip point by ~70mV
0 = Disables decrease of ramp comparator trip point (Default)
1 = Enables decrease of ramp comparator trip point
R/W 0000
Provides capability to mask incoming sample triggers to Front End Control
0 = EADC conversion initiated on every received sample trigger (Default)
1 = EADC conversion initiated once every 2 received sample triggers
2 = EADC conversion initiated once every 3 received sample triggers
....
15 = EADC conversion initiated once every 16 received sample triggers
R/W 0
Enable synchronization of switched cap front end counter to Switching Cycle Frame
boundary
0 = Switch Cap Front End Counter not synchronized to frame (Default)
1 = Switch Cap Front End Counter synchronized to frame boundary
R/W 0
Force reset of Switched Cap Front End Counter
0 = Switch Cap Front End Counter operational (Default)
1 = Switch Cap Front End Counter reset
R/W 0000
Configures initial Switched Cap Front End Counter value out of reset or at start of
switching cycle in Peak Current mode
R/W 0
Enables EADC Data Inversion on data to filter module
0 = EADC Data is not inverted (Default) 1 = EADC Data Inverted
Copyright © 2016, Texas Instruments Incorporated
26 25
R/W-0
19
SCFE_CNT_INIT
11 10
AVG_SPATIAL AVG_MODE_SEL
_EN
R/W-0
3 2
SCFE_GAIN SCFE_CLK
_FILTER_SEL _DIV_2
R/W-1 R/W-1
Description
Front End Control Registers
24
SAMP_TRIG_SCALE
R/W-0000
16
R/W-0000
9 8
EADC_MODE
R/W-00 R/W-000
1 0
SCFE_ENA EADC_ENA
R/W-1 R/W-1
Front End
133