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DPWM Control Register 0 (DPWMCTRL0)
CBC_SYNC_CUR_LIM_EN is used to control the slave sync. If this bit is set, the slave sync is advanced
during current limit. This is not used in any topology configuration at this time. If this bit is set, the sync out
pulse from the DPWM will occur if the CBC fault occurs. If the CBC fault does not occur during a period,
the sync pulse will occur according to the normal setting of the sync control bit fields.
For more information on cycle by cycle current limit, refer to
2.15.4 Multi Mode On/Off
The MULTI_MODE_CLA_A_OFF and MULTI_MODE_CLA_B_OFF bits dictate which calculation is used
for each DPWM pin in multi mode only. In other modes they should not be set. If the bit is cleared, the on-
time of the DPWM pin is controlled by the Filter output. If the bit is set, then the on-time is controlled by
the Event registers.
The AMS registers only have MULTI_MODE_CLA_B_OFF, they do not have
MULTI_MODE_CLA_A_OFF.
2.15.5 Minimum Duty Mode
The MIN_DUTY_MODE bits select how the DPWM handles minimum duty cycle limits.
•
0 Default - Filter output is passed directly through to the DPWM
•
1 - Filter value passed through if above minimum. If below minimum, no pulse from DPWM
•
2 - Filter value passed through if above minimum. If below minimum, DPWM pulse width = minimum
value
There are two registers setting minimum duty and hysteresis:
DPWMMINDUTYLOW
DPWMMINDUTYHI
The Low register sets the point at which the minimum duty mode will take effect as the duty drops. In
mode 2, it also sets the minimum duty.
The High register sets the point at which minimum duty mode is exited as the duty goes up.
These bits are not duplicated in the AMS registers.
These two graphs show modes 1 and 2 with PMMINDUTYLOW at 30, and DPWMMINDUTYHI at 70.
56
Digital Pulse Width Modulator (DPWM)
Copyright © 2016, Texas Instruments Incorporated
Chapter
6.
SNIU028A – February 2016 – Revised April 2016
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