Texas Instruments UCD3138 Technical Reference Manual page 388

PMBus Interface Registers Reference
Table 10-9. PMBus Status Register (PMBST) Register Field Descriptions (continued)
Bit Field
10 SLAVE_ADDR_
READY
9 CLK_HIGH_
DETECTED
8 CLK_LOW_
TIMEOUT
7 PEC_VALID
6 NACK
5 EOM
4 DATA_REQUEST
3 DATA_READY
2-0 RD_BYTE_
COUNT
388
PMBus Interface/I2C Interface
Type Reset
R 0
Slave Address Ready
0 = Indicates no slave address is available for reading
1 = Slave address ready to be read from Receive Data Register (Bits 6:0)
R 0
Clock High Detection Status
0 = No Clock High condition detected
1 = Clock High exceeded 50us during message
R 0
Clock Low Timeout Status
0 = No clock low timeout detected
1 = Clock low timeout detected, clock held low for greater than 35ms
R 0
PEC Valid Indicator
0 = Received PEC not valid (if EOM is asserted)
1 = Received PEC is valid
R 0
Not Acknowledge Flag Status
0 = Data transmitted has been accepted by receiver
1 = Receiver has not accepted transmitted data
R 0
End of Message Indicator
0 = Message still in progress or PMBus in idle state.
1 = End of current message detected
R 0
Data Request Flag
0 = No data needed by PMBus Interface
1 = PMBus Interface request additional data. PMBus clock stretching enabled to stall
bus until firmware provides transmit data.
R 0
Data Ready Flag
0 = No data available for reading by processor
1 = PMBus Interface read buffer full, firmware required to read data prior to further
bus activity. PMBus clock stretching enabled to stall bus until data is read by
firmware.
R 0
Number of Data Bytes available in Receive Data Register
0 = No received data
1 = 1 byte received. Data located in Receive Data Register, Bits 7-0
2 = 2 bytes received. Data located in Receive Data Register, Bits 15-0
3 = 3 bytes received. Data located in Receive Data Register, Bits 23-0
4 = 4 bytes received. Data located in Receive Data Register, Bits 31-0
Copyright © 2016, Texas Instruments Incorporated
Description
SNIU028A – February 2016 – Revised April 2016
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