Cim Prioritization - Texas Instruments UCD3138 Technical Reference Manual

Central Interrupt Module (CIM)
#pragma SWI_ALIAS (write_firqpr, 8)
void write_firqpr(unsigned long value);
#pragma SWI_ALIAS (write_reqmask, 9)
void write_reqmask(unsigned long value);
#pragma INTERRUPT(software_interrupt,SWI)
void software_interrupt(Uint32 arg1, Uint32 arg2, Uint32 arg3, Uint8 swi_number)
{
//make sure interrupts are disabled
asm(" MRS r3, cpsr ");
asm(" ORR r3, r3, #0xc0 "); // set interrupt disables
asm(" MSR cpsr, r3");
asm(" LDRB R3,[R14,#-1]");
switch (swi_number)
{
...
case 8: //write to fiq/irq program_control_register
CimRegs.FIRQPR.all = arg1;
return;
case 9: //write to fiq/irq program_control_register
CimRegs.REQMASK.all = arg1;
return;
...
default:
}
}
The INTERRUPT pragma enables handling interrupts directly with C code. This pragma specifies that the
function to which it is applied is an interrupt. The type of interrupt is specified by the pragma. The software
interrupt will change the CPU to privilege mode. The SWI_ALIAS pragma tells the function write_friqpr()
and write_reqmask() are software interrupts. Calls to these functions are compiled as software interrupts.
A C code example of calling these functions is shown below.
write_firqpr(0x0C000000);
write_reqmask(0x0C010000); //enable only pwm1cmp, dpwm3 and dpwm4

16.4.5 CIM Prioritization

The CIM prioritizes the received interrupts based upon a hardware and software prioritization scheme. The
software prioritization scheme is user configurable. The CIM can send two interrupt requests to the CPU
simultaneously—one IRQ and one FIQ. If both interrupt types are enabled at the CPU, then the FIQ has
greater priority and is handled first. The hardware prioritization scheme sends the highest numbered active
channel (in each FIQ and IRQ interrupt request) to the CPU. Within the FIQ and IRQ classes of interrupts,
the highest channel has the highest priority interrupt. The CIM sends the highest priority interrupt of both
the IRQ and FIQ classes of interrupt requests to the CPU.
16.4.6 CIM Operation
When the CPU recognizes an interrupt request and responds, the program counter jumps to the
appropriate interrupt vector. The interrupt vector is typically a branch statement to an interrupt table. The
interrupt table reads the pending interrupt from a vector offset register (FIQIVEC.7:0 for FIQ interrupts and
IRQIVEC.7:0 for IRQ interrupts).
The following is an example of how such interrupt service routine needs to be written. In this example two
analog comparator interrupts, one DPWM end of period interrupt and two digital fault input pins are all
mapped toward the fast interrupt.
506
Control System Module
// get psr
// restore psr
// get swi number into R3 as fourth operand
// handle flash write/erase and ROM backdoor first
break;
//make them all irqs except dpwm4 and dpwm3.
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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