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Memory Controller – MMC Registers Reference
15.1 Memory Controller – MMC Registers Reference
All MMC control Registers have the following attributes:
•
16-bit width
•
Addresses placed on word boundaries
•
16-bit data is placed on the least significant data bus D[15:0]
•
Only half-word writes are permitted
•
Registers are readable in any mode, but writeable only in privilege mode
15.1.1 Static Memory Control Register (SMCTRL)
Address FFFFFD00
13
12
11
LEAD
R/W-00
R/W-000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-5. Static Memory Control Register (SMCTRL) Register Field Descriptions
Bit
Field
13-12
LEAD
11-9
TRAIL
8
Reserved
7-4
ACTIVE
3
ENDIAN
2
Reserved
468
Memory
Figure 15-1. Static Memory Control Register (SMCTRL)
9
8
TRAIL
Rsvd
R-0
Type
Reset
R/W
00
Address setup time cycles (write operations)
00 = No setup time required (Default)
01 = Write strobe is delayed one cycle
10 = Write strobe is delayed two cycles
11 = Write strobe is delayed three cycles
R/W
000
Number of Trailing wait states. Determine the trailing wait states after read and write
operations to the memory associated with the chip select corresponding to the wait
states.
R
0
R/W
0000
Active Wait states (both read/write operations)
0000 = 0 Wait states (Default)
0001 = 1 Wait states
0010 = 2 Wait states
0011 = 3 Wait states
0100 = 4 Wait states
0101 = 5 Wait states
0110 = 6 Wait states
0111 = 7 Wait states
1000 = 8 Wait states
1001 = 9 Wait states
1010 = 10 Wait states
1011 = 11 Wait states
1100 = 12 Wait states
1101 = 13 Wait states
1110 = 14 Wait states
1111 = 15 Wait states
R
0
Endian Mode Identification
0 = CPU configured in big endian mode
1 = CPU configured in little endian mode
R
0
Copyright © 2016, Texas Instruments Incorporated
7
4
ACTIVE
R/W-0000
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
3
2
1
ENDIAN
Rsvd
WIDTH
R-0
R-0
R/W-00
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