Texas Instruments UCD3138 Technical Reference Manual page 125

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Table 3-3. Ramp Control Register (RAMPCTRL) Register Field Descriptions (continued)
Bit Field
12 RAMP_SAT_EN
11 RAMP_COMP
_INT_EN
10 RAMP_DLY
_INT_EN
9 PREBIAS_INT_EN R/W
8 PCM_START_SEL R/W
7 SYNC_FET_EN
6-5 MASTER_SEL
4 SLAVE_COMP
_EN
3 SLAVE_DELAY
_EN
2 CONTROL_EN
1 FIRMWARE
_START
0 RAMP_EN
SNIU028A – February 2016 – Revised April 2016
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Type Reset
R/W 0
Enables addition or subtraction of DAC Saturation Step when EADC is in saturation.
0 = DAC Saturation Step logic is disabled, DAC incremented/decremented by value
calculated by Ramp logic when EADC is in saturation (Default)
1 = DAC Saturation Step logic is enabled, DAC incremented/decremented by value
stored in DAC Saturation Step register when EADC is in saturation
R/W 0
Enables Ramp I/F Interrupt when soft-start/power-down ramp procedure is complete
0 = Soft-start/Power-Down Ramp Complete Interrupt is disabled (Default)
1 = Soft-start/Power-Down Ramp Complete Interrupt is enabled
R/W 0
Enables Ramp I/F Interrupt when ramp delay procedure is complete
0 = Soft-start/Power-Down Ramp Delay Complete Interrupt is disabled (Default)
1 = Soft-start/Power-Down Ramp Delay Complete Interrupt is enabled
0
Enables Ramp I/F Interrupt when Pre-Bias procedure is completed
0 = Pre-bias Complete Interrupt is disabled (Default)
1 = Pre-bias Complete Interrupt is enabled
0
Peak Current Mode Ramp Start Value Select
0 = Ramp starts from value programmed in DAC_VALUE bits in
EADC_DAC_VALUE Register (Default)
1 = Ramp starts from filter output selected by PCM_FILTER_SEL bits in Loop Mux
register PCMCTRL
R/W 0
Enables SyncFET Ramp Operation
0 = SyncFET Ramp Operation disabled (Default)
1 = SyncFET Ramp Operation enabled
R/W 00
Selects Master Ramp I/F in slave mode
0 = Front End Control 0 acts as master (Default)
1 = Front End Control 1 acts as master
2 = Front End Control 2 acts as master
R/W 0
Enables syncing of ramp start to Master Ramp I/F Complete pulse
0 = Ramp initiated by Master Ramp Complete pulse disabled (Default)
1 = Ramp initiated by Master Ramp Complete pulse enabled
R/W 0
Enables syncing of ramp start to Master Ramp I/F Delay Complete pulse
0 = Ramp initiated by Master Ramp Delay Complete pulse disabled (Default)
1 = Ramp initiated by Master Ramp Delay Complete pulse enabled
R/W 0
Enables PMBus Control line to initiate ramp
0 = PMBus Control does not initiate ramp (Default)
1 = PMBus Control initiates ramp
R/W 0
Ramp start bit, self-clearing by ramp logic
0 = No ramp sequence initiated by firmware (Default)
1 = Ramp sequence initiated by firmware
R/W 0
Enable Ramp Logic (Pre-biasing should be disabled before asserting ramp, bit 16 of
Pre-Bias Control Register)
0 = No soft start or power-down ramp controlled by hardware (Default)
1 = Enables hardware control of soft start or power-down ramp
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Front End Control Registers
Description
125
Front End