Watchdog Timer Example - Texas Instruments UCD3138 Technical Reference Manual

Watchdog Timer Example

11.18 Watchdog Timer Example
In normal watchdog operation, the watchdog is set up to reset the CPU if it makes it to a full count. The
firmware is designed to write a 1 to the CNT_RESET bit frequently, so that the watchdog should never
reach a full count unless some fault causes the firmware to stop executing properly.
Initialization of the watchdog is very simple:
TimerRegs.WDCTRL.bit.CNT_RESET = 1;
TimerRegs.WDCTRL.bit.WDRST_EN = 1;
TimerRegs.WDCTRL.bit.CPU_RESET_EN = 1; //Enable resetting of CPU is watchdog overflows
TimerRegs.WDCTRL.bit.PROTECT = 0;
Then just repeat the two statements below frequently enough in the code to prevent the watchdog counter
from overflowing:
TimerRegs.WDCTRL.bit.CNT_RESET = 1;
If a faster watchdog timeout is desired, simply write to the WD_PERIOD bitfield:
TimerRegs.WDCTRL.bit.WD_PERIOD = 2;
The default value for WD_PERIOD is 0x7f, which will give an approximate 2.2second watchdog.
11.19 Warnings for Watchdog Status Register
Normally there is no need to read the status, but if there is, some precautions should be taken. The
Watchdog Status Register is a clear on read register. The Watchdog is asynchronous to the CPU. On rare
instances, it is possible to read from the register at exactly the right time and read a 0 even though the bit
has been set and then cleared by the read.
To avoid this issue, set the interrupt enable bits in the WDCTRL register, even if the interrupts are not
going to be used. Then poll the interrupt bits in the CIM to determine when the WD bits are set. Then it is
safe to read from the WD status register to clear the bits, which will also clear the CIM bits.
Additionally, please note the following:
• the WAKE_EV_INT will be set at the halfway point and cleared on read of Watchdog Status Register.
• all three bits in the WDST register may be set upon power up reset, so they should be read from in
order to clear them before any polling operation begins.
• any bitwise read actually reads from the entire register and will clear all the bits which are set. So if
sampling of multiple bits is desired, copy the register into a variable and examine the bits individually
there.
11.20 System Fault Recovery Basics
There is a register in the System Module – SYSESR – System Exception Status Register – which saves
the reset cause through the reset. There is a bit for every event except the watchdog timer.
It is possible to look at this register when the program is entered and determine if the reset was caused by
the watchdog timer, or some other cause, such as an illegal address access. Often if a problem occurs
with firmware execution, some other fault will occur before the watchdog timer times out. So if a reset
occurs and none of the bits are set, then the cause is the watchdog timer.
To use this register, examine it when the program is first started. Do whatever processing is necessary,
save the reset cause if desired, and then clear the register. In this way, it will be possible to tell the next
reset cause. If the register is not cleared by the program, there may be two bits set the next time, making
it impossible to determine the cause of the newest reset.
All resets, regardless of the cause, will reset all of the peripherals to their default state, so most outputs
will go to inputs and so on. This will generally have the effect of shutting down any power supply that is
being controlled by the device.
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Timer Module Overview
//make sure counter is cleared
//Enable watchdog
//enable protected watchdog
//make sure counter is cleared
// fast watchdog
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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