Global Enable Register (Glben) - Texas Instruments UCD3138 Technical Reference Manual

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5.14.21 Global Enable Register (GLBEN)

Address 00020050
10 9
FE_ FE_ FE_
CTRL2 CTRL1 CTRL0
_EN _EN _EN
R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-22. Global Enable Register (GLBEN)Register Field Descriptions
Bit Field
10 FE_CTRL2_EN
9 FE_CTRL1_EN
8 FE_CTRL0_EN
7-4 Reserved
3 DPWM3_EN
2 DPWM2_EN
1 DPWM1_EN
0 DPWM0_EN
SNIU028A – February 2016 – Revised April 2016
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Figure 5-22. Global Enable Register (GLBEN)
8 7
Reserved
R-0000
Type Reset
R/W 0
Global Firmware Enable for Front End Control 2 Module
0 = Front End Control 2 Module Disabled (Default)
1 = Front End Control 2 Module Enabled
R/W 0
Global Firmware Enable for Front End Control 1 Module
0 = Front End Control 1 Module Disabled (Default)
1 = Front End Control 1 Module Enabled
R/W 0
Global Firmware Enable for Front End Control 0 Module
0 = Front End Control 0 Module Disabled (Default)
1 = Front End Control 0 Module Enabled
R 0000
R/W 0
Global Firmware Enable for DPWM 3 Module
0 = DPWM 3 Module Disabled (Default)
1 = DPWM 3 Module Enabled
R/W 0
Global Firmware Enable for DPWM 2 Module
0 = DPWM 2 Module Disabled (Default)
1 = DPWM 2 Module Enabled
R/W 0
Global Firmware Enable for DPWM 1 Module
0 = DPWM 1 Module Disabled (Default)
1 = DPWM 1 Module Enabled
R/W 0
Global Firmware Enable for DPWM 0 Module
0 = DPWM 0 Module Disabled (Default)
1 = DPWM 0 Module Enabled
Copyright © 2016, Texas Instruments Incorporated
Loop Mux Registers Reference
4 3 2
DPWM3 DPWM2
_EN _EN
R/W-0 R/W-0
Description
1 0
DPWM1 DPWM0
_EN _EN
R/W-0 R/W-0
217
Loop Mux