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UART Frame Format
12.1 UART Frame Format
The UART uses a programmable frame format. All frames consist of the following:
•
One start bit
•
One to eight data bits
•
Zero or one parity bit
•
One or two stop bits
The frame format for both the transmitter and receiver is programmable through the bits in the
UARTCTRL0 register. Both receive and transmit data is in non-return to zero (NRZ) format, which means
that the transmit and receive lines are at logic high when idle.
Each frame transmission begins with a start bit, in which the transmitter pulls the SCI line low (logic low).
Following the start bit, the frame data is sent and received least significant bit first (LSB).
A parity bit is present in every frame when the PARITY ENA bit (UARTCTRL0.5) is set. The value of the
parity bit depends on the number of one bits in the frame and whether odd or even parity has been
selected via the PARITY bit (UARTCTRL0.6).
All frames include one stop bit, which is always a high level. This high level at the end of each frame is
used to indicate the end of a frame to ensure synchronization between communicating devices. Two stop
bits are transmitted if the STOP bit (UARTCTRL0.7) is set. The example shown in Figure below uses one
stop bit per frame.
12.2 Asynchronous Timing Mode
Asynchronous timing mode is the only mode supported in UCD3138. In the asynchronous timing mode,
each bit in a frame has a duration of 8 UART baud clock periods. Each bit therefore consists of 8 samples
(one for each clock period).
When the UART is using asynchronous mode, the baud rates of all communicating devices must match as
closely as possible. Receive errors result from devices communicating at different baud rates.
With the receiver in the asynchronous timing mode, the UART detects a valid start bit if the first four
samples after a falling edge on the SCI_RX pin are of logic level 0. As soon as a falling edge is detected
on SCI_RX, the UART assumes that a frame is being received and synchronizes itself to the bus.
The UART module has been designed to provide some protection from noise causing unintended start bits
or incorrect data. Without protection, a noise spike that brings an idle receive line low may be interpreted
as a start bit.
The UART prevents this by requiring a start bit to bring the SCI_RX line low for at least four contiguous
UART baud clock periods. If any of the receive samples during the first four UART baud clock periods is
not a logic low, then the UART does not consider this a start bit and considers the receive line idle.
When another falling edge is detected, the UART checks for a valid, noise-free start bit. When a valid start
bit is detected, the UART determines the value of each bit by sampling the SCI_RX line value during the
fourth, fifth, and sixth UART baud clock periods. A majority vote of these samples is used to determine the
value stored in the UART receiver shift register.
By sampling in the middle of the bit, the UART reduces errors caused by propagation delays and rise and
fall times. By taking a majority vote, the UART reduces the likelihood of data corruption caused by data
line noise.
Figure 12-2
timing mode.
422
UART Overview
Figure 12-1.
illustrates how the receiver samples a start bit and a data bit in asynchronous
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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