24-Bit Output Compare Channel 1 Control Register (T24Cmpctrl1) - Texas Instruments UCD3138 Technical Reference Manual

www.ti.com

11.21.9 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1)

Address FFF7FD30
Figure 11-12. 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1)
CMP_INT_ENA
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-9. 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1) Register Field
Bit Field
1 CMP_INT_ENA
0 CMP_INT_FLAG
SNIU028A – February 2016 – Revised April 2016
Submit Documentation Feedback
1
R/W-0
Type Reset
R/W 0
Output Compare Channel Interrupt
0 = Disables Output Compare Channel Interrupt (Default)
1 = Enables Output Compare Channel Interrupt
R/W 0
Indicates a valid output compare event. Bit can be cleared by writing a '1' to the bit
or by rewriting the 24-bit Output Compare Channel Data Register. If a clear and
compare event occur at the same time, the flag will remain high (set has priority
versus clear).
0 = No compare event since last clear
1 = Compare event since last clear
Copyright © 2016, Texas Instruments Incorporated
CMP_INT_FLAG
Descriptions
Description
Timer Module Register Reference
0
R/W-0
Timer Module Overview
413