Pwmx 16-Bit Compare Channel 0-1 Data Register (T16Pwmxcmpydat); Pwmx 16-Bit Compare Channel 0-1 Data Register (T16Pwmxcmpydat) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

Timer Module Register Reference

11.21.12 PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT)

Address FFF7FD3C – 16-bit PWM0 Compare Channel 0 Data Register
Address FFF7FD40 – 16-bit PWM0 Compare Channel 1 Data Register
Address FFF7FD60 – 16-bit PWM1 Compare Channel 0 Data Register
Address FFF7FD64 – 16-bit PWM1 Compare Channel 1 Data Register
Address FFF7FD74 – 16-bit PWM2 Compare Channel 0 Data Register
Address FFF7FD78 – 16-bit PWM2 Compare Channel 1 Data Register
Address FFF7FD88 – 16-bit PWM3 Compare Channel 0 Data Register
Address FFF7FD8C – 16-bit PWM3 Compare Channel 1 Data Register
Figure 11-15. PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-12. PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT) Register Field
Bit Field
15-0 CMP_DAT
416
Timer Module Overview
R/W-0000 0000 0000 0000
Type Reset
R/W 0000
Contains the 16-bit compare value. When in PWM mode, the value in the
0000
T16PWMxCMPyDAT is loaded after a match with the PWMx Counter Data Register.
0000
When in OC mode, it has to be written by the CPU. The mode is controlled by the bit
0000
SHADOW in the PWMx/Dual Compare Control Register. If both Registers
T16PWMxCMP0DAT and T16PWMxCMP1DAT contain the same value, the interrupt
and pin behavior is controlled by output compare channel 0 (T16PWMxCMP0DAT
has priority over T16PWMxCMP1DAT).
Copyright © 2016, Texas Instruments Incorporated
CMP_DAT
Descriptions
Description
SNIU028A – February 2016 – Revised April 2016
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