Program Flash Control Register (Pflashctrl); Pflashctrl Addresses; Program Flash Control Register (Pflashctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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15.2.20 Program Flash Control Register (PFLASHCTRL)

11 10 9
BUSY Reserved PAGE_
ERASE
R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-29. Program Flash Control Register (PFLASHCTRL) Register Field Descriptions
Bit Field
11 BUSY
10 Reserved
9 PAGE_ERASE
8 MASS_ERASE
7-5 Reserved
4-0 PAGE_SEL
SNIU028A – February 2016 – Revised April 2016
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Table 15-28. PFLASHCTRL Addresses
Part Number
3138
3138064
3138A64
3138128
Figure 15-24. Program Flash Control Register (PFLASHCTRL)
8 7
MASS_ Reserved
ERASE
R/W-0 R-000
Type Reset
R 0
Program Flash Busy Indicator
0 = Program Flash available for read/write/erase access
1 = Program Flash unavailable for read/write/erase access
R 0
R/W 0
Program Flash Page Erase Enable
0 = No Page Erase initiated on Program Flash (Default)
1 = Page Erase on Program Flash enabled. Page erased is based on PAGE_SEL
(Bits 4-0). Interlock Key must be set in Program Flash Interlock Register
(Section
Page Erase cycle.
R/W 0
Program Flash Mass Erase Enable
0 = No Mass Erase initiated on Program Flash (Default)
1 = Mass Erase of Program Flash enabled. Interlock Key must be set in Program
Flash Interlock Register
cleared upon completion of Mass Erase cycle.
R 000
R 00000
Selects page to be erased during Page Erase Cycle
Copyright © 2016, Texas Instruments Incorporated
DEC – Address Manager Registers Reference
Addresses
FFFFFE90
FFFFFE90 (PFLASHCTRL_1)
FFFFFE9C (PFLASHCTRL_2)
FFFFFE90 (PFLASHCTRL_0)
FFFFFE9C (PFLASHCTRL_1)
FFFFFE90 (PFLASHCTRL_0)
FFFFFE9C (PFLASHCTRL_1)
FFFFFEA0 (PFLASHCTRL_2)
FFFFFEA4 (PFLASHCTRL_3)
5 4
Description
16.1.8) to initiate Page Erase cycle. This bit is cleared upon completion of
(Section 16.1.8) to initiate Mass Erase cycle. This bit is
0
PAGE_SEL
R-00000
Memory
493