Ucs3138 Digital Comparators Control Block Diagram; Digital Comparators - Texas Instruments UCD3138 Technical Reference Manual

Digital Comparators

8.9 Digital Comparators
The ADC12 control module provides 6 Digital comparators that can be utilized to compare either raw ADC
data or averaged ADC data against programmable high and low thresholds. The first 6 conversion result
registers (ADC Result Registers 0-5) or the first 6 conversion averaged result registers (ADC Averaged
Result Registers 0-5) of the ADC sequence are tied to the 6 Digital Comparators. Therefore, for any
signals requiring auto limit monitoring, the user must use these 6 ADC conversion slots for monitoring of
those signals. All 12 bits of conversion result are used for comparison. The Digital Comparators provide
12 status bits for monitoring, two from each ADC result comparison. These status bits indicate whether the
ADC result is higher or equal to the Limit High threshold or if it is lower or equal to the Limit Low threshold.
12
Result 0
12
Result 5
Figure 8-10. UCS3138 Digital Comparators Control Block Diagram
NOTE: The ADCCOMPRESULT provide both raw (non-latched) and latched comparator output
results. There is no need to enable the bits DCOMPx_LO_INT_EN or DCOMPx_UP_INT_EN
in order for the DCOMPx_LO_INT or DCOMPx_UP_INT to trip.
The latched results are clear on read and the first read of the ADCCOMPRESULT will clear all latched
values. For example, both statements below will clear all of the latched results.
int scrap;
scrap = AdcRegs.ADCCOMPRESULT.all;
or
scrap = AdcRegs.ADCCOMPRESULT.bit.DCOMP3_LO_INT;
304
ADC12 Overview
12
R0-LimH
12
R0-LimL
12
R5-LimH
12
R5-LimL
Copyright © 2016, Texas Instruments Incorporated
LimH Result 0
≤
Limit
logic
Result 0
≤
LimH Result 5
≤
Limit
logic
Result 5 ≤
SNIU028A – February 2016 – Revised April 2016
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LimL
LimL