Timing Parameters From Timing Diagrams; Simple Timing Parameters (No Timing Diagram); Effect Of Man_Slave_Ack Bit On Eom Handling - Texas Instruments UCD3138 Technical Reference Manual

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t – Time from PMBUS_DATA low for Start signal to UNIT_BUSY bit
START
set
t – Time from PMBUS_CLK low on bit 8 to SLAVE_ADDR_READY bit
SAR
set
t – Time from PMBUS_CLK low on bit 8 of address byte to
DREQ1
DATA_REQUEST bit set
t – Time from write to ACK bit until UCD releases clock stretch
ACKWRITE
t – Time from write to ACK bit until DATA_REQUEST bit is set
DREQ2
t – Time from PMBUS_DATA low for Repeated Start to
RPTSTRT
RPT_START bit set
t – Time from PMBUS_CLK low on bit 8 of read byte to
DREQ3
DATA_REQUEST bit set
t – Time from PMBUS_CLK low on bit 8 to SLAVE_ADDR_READY
TXBWRITE
bit set
t – Time from PMBUS_CLK low on bit 8 to DATA_RDY bit set
DRDY
t – Time from PMBUS_CLK high for Stop signal to EOM and
EOM
DATA_RDY bits set, as well as PEC VALID and RD_BYTE_COUNT
loaded with correct value.
PMBus/I2C edge which triggers change
SCL rise or fall
SDA rise or fall
CONTROL rise or fall
ALERT rise or fall
CONTROL edge specified by CNTL_INT_EDGE
ALERT falling edge
SCL and SDA high for nominal 50 usec
PMBST Bit Set to Interrupt Trigger

10.6 Effect of MAN_SLAVE_ACK bit on EOM Handling

Even though MAN_SLAVE_ACK primarily affects the handling of the beginning of the message, it also
changes how the end of the message is handled.
In both modes, the PMBus hardware is designed to stretch the clock until the firmware is done processing
the previous message.
When MAN_SLAVE_ACK is low, the firmware must ACK after the EOM. This tells the hardware that it is
OK to ack the next address automatically and put the new address value into the PMBHSA. The EOM
should not be ACKed until the firmware has read the PMBHSA for the message.
The next bit set in the status register will be either DATA_READY or DATA_REQUEST.
SNIU028A – February 2016 – Revised April 2016
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Table 10-2. Timing Parameters from Timing Diagrams
Parameter
Table 10-4. Simple Timing Parameters (No Timing Diagram)
Interval
Copyright © 2016, Texas Instruments Incorporated
Effect of MAN_SLAVE_ACK bit on EOM Handling
Min
366
488
427
427
366
427
427
488
427
Table 10-3.
Bit Field
Changed
SCL_RAW set
or clear
SDA_RAW set
or clear
CONTROL_RA
W set or clear
ALERT_RAW
set or clear
CONTROL_EDG
E
ALERT_EDGE
BUS_FREE set
Max Units
470 ns
605 ns
538 ns
538 ns
ns
470 ns
538 ns
538 ns
605 ns
538 ns
Min(ns) Max(ns)
244 336
244 336
244 336
244 336
244 336
244 336
122 202
Min(ns) Max(ns)
61 67
PMBus Interface/I2C Interface
371