Dac Ramp Start, Interrupts, Start Delay; Rampstat Register; Dac Ramp When Eadc Is Saturated; Using Ramp Module For Peak Current Mode - Texas Instruments UCD3138 Technical Reference Manual

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3.3.4 DAC Ramp Start, Interrupts, Start Delay

DAC Ramp start is controlled by bits in the Ramp Control Register (RAMPCTRL) The DAC Ramp can be
started by several events, listed above. These are all clearly described in
also contains a setting for pre-ramp delay, and bits which control interrupts for ramp events.
To enable the Ramp, it is also necessary to set the RAMP_EN bit in the RAMPCTRL register.

3.3.5 RAMPSTAT Register

The RAMPSTAT register has bits which indicate ramp completion and other ramp status events. The
RAMPCTRL register can also be used to enable interrupts for ramp status events.

3.3.6 DAC RAMP when EADC is Saturated

DACSATSTEP configures the DAC increment/decrement value when the EADC is saturated during the
Automated Ramp.
If the EADC is saturated high (Verror = Vref – Vsense), the DAC setpoint is lowered by the DACSATSTEP
value. The decrement will continue until the EADC is out of saturation. This decrement when the EADC is
in saturation occurs periodically when the DAC would be updated with a new DAC value during the ramp.
If the EADC is saturated low, the DAC setpoint is incremented by the DACSATSTEP value. The increment
will continue until the EADC is out of saturation. This increment when the EADC is in saturation occurs
periodically when the DAC would be updated with a new DAC value during the ramp.
If the step value is carefully chosen, this mode may help to keep the EADC from saturating during a ramp
up. It may, however, make the ramp timing undeterministic and non-monotonic.

3.3.7 Using Ramp Module for Peak Current Mode

The ramp module is also used for Analog Peak Current Mode (APCM). Normally the PCM_START_SEL
bit is set so that a filter output is used to drive the starting point of the ramp. The ramp end point is set to a
low value so that the ramp will always go downward.
In this mode, the ramp trigger simply starts the ramp. The step comes from the Front End at a 32
nanosecond rate. There is a comparator in the Front End. This comparator compares the ramp value (in
the DAC) to the EADC input value. When the EADC input exceeds the ramp value, the APCM fault output
of the Front End goes active. This bit can be sent to the DPWM pins via the Loop Mux and Fault Mux.
The Front End drawing omits it for simplicity, but the DAC (and the input to the EADC amplifier) are
actually differential. The PCM comparator, however, is single ended. So there is a differential to single
ended converter between the DAC and the PCM comparator. This comparator must be enabled for PCM
to work. The D2S_COMP_EN bit in the EADCCTRL register performs this function.
For additional information consult the reference firmware provided with UCD3138PSFBEVM-029 EVM and
TI application note on Phase Shift Full Bridge (Peak Current mode control) implementation.
SNIU028A – February 2016 – Revised April 2016
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Table 3-2. (continued)
Hidden Step Register
0x000500
0x000600
0x000700
0x000800
0x000900
0x000A00
Copyright © 2016, Texas Instruments Incorporated
DAC Register
0x0001
0x0001
0x0001
0x0002
0x0002
0x0002
Section 3.7. The same register
Ramp Module
121
Front End