Transmit Interrupt - Texas Instruments UCD3138 Technical Reference Manual

Transmit Interrupt

Additionally, the transmitter uses the TXRDY flag (UARTTXST.2) to indicate that the transmitter is ready
for new data to be written that will be sent to the bus.
Transmit, receive, and error interrupts are enabled or disabled through separate interrupt-enable bits.
When not enabled, the interrupts are not asserted; however, polled operation of the UART is still possible
because the interrupt flags continue to indicate module events.
The UART module generates three interrupt requests to the UCD3138 system module: one each for
transmitter, receiver, and error interrupts. Each of these interrupts must also be configured in the
UCD3138 system module before operation.
Normally, the error interrupt has the highest priority, the receiver interrupt has the next highest priority, and
the transmitter generally has the lowest priority.
This prioritizing scheme reduces the possibility of missed error conditions and receiver overrun. For
interrupt priority levels on a specific device, consult the UCD3138 device datasheet.
12.4 Transmit Interrupt
This section describes how a CPU interrupt can be initiated by a transmit ready condition.
The transmit ready (TXRDY) flag is set when the UART transfers the contents of UARTTXBUF to the shift
register, UARTTXSHF. The TXRDY flag indicates that UARTTXBUF is ready to be loaded with more data.
In addition, the UART sets the TX EMPTY bit if both the UARTTXBUF and UARTTXSHF registers are
empty.
Transmit interrupts are enabled by the TX_INT_ENA (UARTCTRL3.3) bit. If the TX_INT_ENA bit
(UARTCTRL3.3) is set, then a transmit interrupt is generated when the TXRDY flag goes high.
Writing data to the UARTTXBUF register clears the TXRDY bit. When this data has been moved to the
UARTTXSHF register, the TXRDY bit is set again.
The interrupt request can be suspended by clearing the TX_INT_ENA bit; however, when the
TX_INT_ENA bit is again set to 1, the TXRDY interrupt is asserted again.
The transmit interrupt request can be eliminated until the next series of values is written to UARTTXBUF
by disabling the transmitter via the TXENA bit (UARTTXST.0 = 0), an UART software reset, or by a device
hardware reset.
12.5 Receive Interrupt
The receive ready (RXRDY) flag is set when the UART transfers newly received data from SCIRXSHF to
UARTRXBUF
The RXRDY flag therefore indicates that the UART has new data to be read. Receive interrupts are
enabled by the RX_INT_ENA bit.
If the RX_INT_ENA bit (UARTCTRL3.4) is set when the UART sets the RXRDY flag, then a receive
interrupt is generated.
12.6 Error Interrupts
The UCD3138's UART module provides hardware indication of error conditions to provide information
about the status of module operation. According to the data being assembled by the receiver, the UART
monitors the data received for errors and sets the parity error (PE), framing error (FE), and/or the break-
detect (BRKDT) flag when these conditions are detected.
In addition, the UART sets the overrun error (OE) flag if a transfer of new data from UARTRXSHF to
UARTRXBUF overwrites unread data in UARTRXBUF. (If both overrun and parity errors occur, only the
overrun error flag is set.)
The UART sets the wake-up flag (WAKEUP) if bus activity on the RX line either prevents power-down
mode from being entered, or RX line activity causes an exit from power-down mode. Each of these flags is
located in the receiver status (UARTRXST) register.
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UART Overview
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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