Peripheral Control Register (Pctrl); Peripheral Control Register (Pctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

www.ti.com

15.1.3 Peripheral Control Register (PCTRL)

Address FFFFFD30
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-7. Peripheral Control Register (PCTRL) Register Field Descriptions
Bit Field
0 PUBF_ENA
SNIU028A – February 2016 – Revised April 2016
Submit Documentation Feedback
Figure 15-3. Peripheral Control Register (PCTRL)
Type Reset
R/W 0
Write buffer enable. When this bit is set to 1, the memory controller latches the data
and control signals in the first cycle for write operations to the memories and
peripherals on the expansion bus and lets the CPU perform other operations.
However, the CPU starts a wait state if there is another request before the memory
controller finishes.
0 = Write buffer disabled (Default)
1 = Write buffer enabled
Copyright © 2016, Texas Instruments Incorporated
Memory Controller – MMC Registers Reference
0
PBUF_ENA
R/W-0
Description
471
Memory