Filter Control Register (Filterctrl); Filter Control Register (Filterctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

Filter Registers Reference

4.11.2 Filter Control Register (FILTERCTRL)

Address 00060004 – Filter 2 Control Register
Address 00090004 – Filter 1 Control Register
Address 000C0004 – Filter 0 Control Register
15 14
KI_ADDER PERIOD_MULT
_MODE _SEL
R/W-1 R/W-0
7 6
KD_STALL KI_STALL
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-2. Filter Control Register (FILTERCTRL) Register Field Descriptions
Bit Field
15 KI_ADDER_MODE R/W
14 PERIOD_MULT
_SEL
13-12 OUTPUT_MULT
_SEL
11-9 YN_SCALE
8 NL_MODE
7 KD_STALL
6 KI_STALL
158
Filter
Figure 4-7. Filter Control Register (FILTERCTRL)
13 12
OUTPUT_MULT_SEL
R/W-00
5 4
KP_OFF KD_OFF
R/W-0 R/W-0
Type Reset
1
Configures addition of Xn and Xn-1 in Integral branch
0 = Only Xn used for addition (Xn + 0)
1 = Xn + Xn-1 used for addition (Default)
R/W 0
Selects output multiplicand used for multiplying with filter output to calculate DPWM
Period value in Resonant Mode
0 = Switching period received from Loop Mux module (Default)
1 = KComp received from Loop Mux module
R/W 00
Selects output multiplicand used for multiplying with filter output to calculate DPWM
Duty value
0 = KComp received from Loop Mux module (Default)
1 = Switching period received from Loop Mux module
2 = Feed-Forward value received from Loop Mux module
3 = Resonant Duty value received from DPWM Module
R/W 000
Controls scaling of Yn value to compensate for filter coefficient scaling
-4 = Filter output (Yn) left shifted by 4
-3 = Filter output (Yn) left shifted by 3
-2 = Filter output (Yn) left shifted by 2
-1 = Filter output (Yn) left shifted by 1
0 = Filter output (Yn) not scaled (Default)
1 = Filter output (Yn) right shifted by 1
2 = Filter output (Yn) right shifted by 2
3 = Filter output (Yn) right shifted by 3
R/W 0
Sets non-linear gain table configuration. Coefficient Bin mapping is controlled by
Coefficient Configuration Register. Limit configuration is controlled by the Filter
Nonlinear Limit Registers (See
0 = Non-symmetric mode (Default)
1 = Symmetric mode
R/W 0
Freezes KD Branch, KD_YN remains at current value
0 = KD_YN recalculated on each filter update (Default)
1 = KD_YN stalled at present value
R/W 0
Freezes KI Branch, KI_YN remains at current value
0 = KI_YN recalculated on each filter update (Default)
1 = KI_YN stalled at present value
Copyright © 2016, Texas Instruments Incorporated
11
YN_SCALE
R/W-000
3 2
KI_OFF FORCE_
START
R/W-0 R/W-0
Description
Section 4.5)
SNIU028A – February 2016 – Revised April 2016
www.ti.com
9 8
NL_MODE
R/W-0
1 0
USE_CPU_ FILTER_EN
SAMPLE
R/W-0 R/W-1
Submit Documentation Feedback