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3.1.3 EADC Triggering, EADC Output to Filter
The EADC is generally triggered by a sample trigger signal from a DPWM module. After this trigger, if
averaging is enabled, additional triggers may come from the averaging module. The EADC can also be
triggered by the Successive Approximation (SAR) module. Multiple DPWMS can be used to trigger a
single EADC at different times in the same period.
Each DPWM module has 2 sample trigger registers to set sample trigger timing. The DPWMs can also
provide oversampling of 2, 4, or 8 samples in coordination with 1 of the 2 sample triggers. See
Section
2.17.5, for more information.
The Sample Trigger Control register in the Loop Mux module controls the routing of sample trigger signals
from the DPWMs to the EADCs. There is a bit in that register for every possible DPWM/Front End
combination. If that bit is set, then the sample trigger from that specific DPWM will be routed to that
specific front end. For example, to use DPWM3 to trigger Front End 2, this is the code:
LoopMuxRegs.SAMPTRIGCTRL.bit.FE2_TRIG_DPWM3_EN = 1;
See
Chapter 5
for more information.
If the EADC is driving a filter, that filter will compute its output at the conclusion of the EADC conversion.
The Filter Mux register in the Loop Mux selects which front ends send data to which filters. For instance to
send the output from Front End 2 to Filter 1:
LoopMuxRegs.FILTERMUX.bit.FILTER1_FE_SEL = 2; //use Front end 2 for filter 1.
See
Chapter 5
for more information.
Sample triggers can also be divided so that the EADC only fires every 1 to 16 sample triggers:
FeCtrl0Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 4; //trigger every 5 sample triggers.
3.1.4 EADC Timing
The EADC takes either 16 or 32 cycles of the 250 MHz high speed clock to complete an analog to digital
conversion. The timing logic runs continuously, producing samples every 64 or 128 ns. This gives
maximum sample rates of 16 MHz and 8 MHz respectively. The sample trigger, when it occurs, takes the
latest sample. It does not trigger the start of a conversion.
To set the EADC speed, use the Switched Cap Front End (SCFE) Divide by 2 (SCFE_DIV_2) bit in the
EADC Control register. Setting the bit divides the sample period by 2. The bit is set by default, giving a
nominal 64 ns sample period. Clearing the bit doubles the period:
FeCtrl0Regs.EADCCTRL.bit.SCFE_CLK_DIV_2 = 0; //clear for 128 ns sample interval.
By default the EADC switched cap filter runs continuously at a fixed rate. If the period is not an integer
multiple of this rate, the sample time could shift around within a 64 nanosecond window.
To avoid this, set the Frame Sync Enable bit:
FeCtrl0Regs.EADCCTRL.bit.FRAME_SYNC_EN = 1;
//resync EADC sampling to frame boundary at start of each frame.
The frame start signal comes from 1 or more DPWMs. DPWM selection is done in the Front End Control
Mux Registers in the Loop Mux. Each Front end has a Front End Control Mux register which controls
many inputs to the Front End, including the frame sync for the EADC sampling reset.
For example, to use DPWM3 frame sync for Front End 2:
LoopMuxRegs.FECTRL2MUX.bit.DPWM3_FRAME_SYNC_EN = 1;
There is a bit which initializes the state machine counter for the front end to a non-zero value. This should
be left at 0, however. Other numbers will cause unexpected results.
FeCtrl0Regs.EADCCTRL.bit.SCFE_CNT_INIT = 0; //leave at 0.
SNIU028A – February 2016 – Revised April 2016
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