Filter Status Register - Texas Instruments UCD3138 Technical Reference Manual

Filter Status Register

Here is an example of a typical use of the Filter Output Stage:
Filter YN (50% Duty) 0x400000 or 4194304
X DPWM Period (100 kHz) 0x9C4 or 2500
=
0x271000000 or 10485760000
Shift right by 19 bits and round: 0
x4E20 or 20000
This result is what goes to the DPWM, with high resolution.
To convert it back to the period scale and check results, we can divide by 16, which is the same as
shifting right by 4 bits. This gives:
0x4e2 or 1250,
which is half the period, so we do get a 50% duty cycle.
4.2 Filter Status Register
The Filter status register has 5 bits.
FILTER_BUSY
YN_LOW_CLAMP
YN_HIGH_CLAMP
KI_YN_LOW_CLAMP
KI_YN_HIGH_CLAMP
The FILTER_BUSY bit is high when the filter is calculating. This calculation time is very short, only a few
instruction cycles. It is very difficult to reliably detect the high time of the Filter Busy bit.
The other bits are written to each time the filter calculation is complete. They reflect the result of the most
recent filter calculation.
4.3 Filter Control Register
The Filter Control Register (FILTERCTRL) has 13 fields. They are used to configure the filter operation.
Filter sources and destinations are set in the Loop Mux registers
KI_ADDER_MODE
PERIOD_MULT_SEL
OUTPUT_MULT_SEL
YN_SCALE
NL_MODE
KD_STALL
KI_STALL
KP_OFF
KD_OFF KI_OFF
FORCE_START
USE_CPU_SAMPLE F
ILTER_EN
148
Filter
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SNIU028A – February 2016 – Revised April 2016
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