Watchdog Control (Wdctrl); Watchdog Control (Wdctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

Timer Module Register Reference

11.21.15 Watchdog Control (WDCTRL)

Address FFF7FD98
14
PERIOD
R/W-1111 1111
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-15. Watchdog Control (WDCTRL) Register Field Descriptions
Bit Field
14-8 PERIOD
7 Reserved
6 PROTECT
5 CPU_RESET_EN
4 WDRST_INT_EN
3 WKEV_INT_EN
2 WKEV_EN
1 WDRST_EN
0 CNT_RESET
420
Timer Module Overview
Figure 11-18. Watchdog Control (WDCTRL)
8
Type Reset
R/W 1111
Configures the time for the watchdog reset.
1111
H'7F ~ 2.2s typical (1.85 min to 2.6 max seconds)(Default)
H'00 ~ 17mstypical (14.5 min to 20.1 max milliseconds)
R 0
R/W 1
Watchdog Protect Bit, Active Low
0 = Watchdog enable bits are protected, only can be cleared by POR.
CPU_RESET_ENA (Bit 5), WDRST_ENA (Bit 2) and WKEV_ENA (Bit 1) are
automatically set high when PROTECT is written low.
1 = Watchdog enable bits can be set by processor (Default)
R/W 0
Enables Watchdog Reset Event to reset the CPU
0 = Watchdog Reset does not reset CPU (Default)
1 = Watchdog Reset does resets CPU
R/W 0
Watchdog Reset Event Interrupt Enable
0 = Disables generation of Watchdog Reset Interrupt (Default)
1 = Enables generation of Watchdog Reset Interrupt
R/W 0
Watchdog Wake Event Interrupt Enable
0 = Disables generation of Watchdog Wake Event Interrupt (Default)
1 = Enables generation of Watchdog Wake Event Interrupt
R/W 0
Watchdog Wake Event Comparator Enable
0 = Disables Watchdog Wake Event Comparator (Default)
1 = Enables Watchdog Wake Event Comparator
R/W 0
Watchdog Reset Event Comparator Enable
0 = Disables Watchdog Reset Event Comparator (Default)
1 = Enables Watchdog Reset Event Comparator
R/W 1
This bit resets the watchdog counters. This bit self clears and if the enables are set,
the counters restart counting.
0 = Watchdog counters enabled (Default)
1 = Watchdog counters reset
Copyright © 2016, Texas Instruments Incorporated
7 6 5
Reserv PROT CPU_ WDRS
ed ECT RESET T_INT_
_EN EN
R-0 R/W-1 R/W-0 R/W-0
Description
SNIU028A – February 2016 – Revised April 2016
www.ti.com
4 3 2 1
WKEV WKEV WDRS
_INT _EN T_EN
_EN
R/W-0 R/W-0 R/W-0
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0
CNT_
RESET
R/W-1