2.15.3 Cycle By Cycle Current Limit Enable - Texas Instruments UCD3138 Technical Reference Manual

DPWM Control Register 0 (DPWMCTRL0)

2.15.3 Cycle by Cycle Current Limit Enable

There are several enable bits related to cycle by cycle current limit:
DPWMCTRL0 contains:
CBC_PWM_C_EN
CBC_PWM_AB_EN
CBC_ADV_CNT_EN
CBC_SYNC_CUR_LIMIT_EN
CBC_BSIDE_ACTIVE_EN
All of these bits, except for CBC_BSIDE_ACTIVE_EN also occur in the AMS registers.
The first two, CBC_PWM_C_EN and CBC_PWM_AB_EN simply enable cycle by cycle current limit for
their respective signals. In all modes, CBC_PWM_EN has an independent effect on DPWMC.
The other bits have no effect on DPWMC The other three bits have different effects in different modes.
Here are the effects:
Normal Mode
In normal mode, a CBC event will cause DPWMA to go low before the time dictated by the CLA. The dead
time for DPWMB will be preserved, so the rising edge of DPWMB will be moved forward by the same
amount as the falling edge of DPWMA.
There are only two options for setting the CBC bits in normal mode:
1. All cleared, no CBC.
2. Set both CBC_PWM_AB_EN and CBC_ADV_CNT_EN to get CBC
CBC_BSIDE_ACTIVE_EN has no effect. Normal mode has some support for negative dead times, as
does the CBC logic. Even negative dead times will be preserved. As seen in
negative dead time, the minimum pulse width on DPWMA will be equivalent to the dead time. To preserve
a negative dead time, the CBC will trigger a rising edge on DPWMB. After the dead time is expired, then
DPWMA will fall.
With a positive dead time, of course, DPWMA will fall with the CBC event, and DPWMB will rise after the
dead time:
54
Digital Pulse Width Modulator (DPWM)
Copyright © 2016, Texas Instruments Incorporated
Figure 2-14, if there is a
SNIU028A – February 2016 – Revised April 2016
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