Interrupt Handling By Cpu - Texas Instruments UCD3138 Technical Reference Manual

Central Interrupt Module (CIM)

16.4.1 Interrupt Handling by CPU

As previously mentioned, the ARM7 CPU provides two vectors for interrupt requests - fast interrupt
requests (FIQ) and normal interrupt requests (IRQ). The CPU may enable these interrupt request
channels individually within the CPSR; CPSR bits 6 and 7 must be cleared to enable the FIQ and IRQ
interrupt requests at the CPU. When both interrupt requests are enabled, the FIQ interrupt request has
higher priority than the IRQ and is handled first.
When the CPU recognizes an interrupt request, the CPSR changes mode to either the FIQ or IRQ mode.
When an IRQ interrupt is recognized, the CPU disables other IRQ interrupts by setting CPSR bit 7. When
an FIQ interrupt is recognized, the CPU disables both IRQ and FIQ interrupts by setting CPSR bits 6 and
7. After the interrupt is recognized by the CPU, the program counter jumps to the appropriate interrupt
vector—0x0018 for IRQ and 0x001C for FIQ.
16.4.2 Interrupt Generation at Peripheral
Interrupts begin when an event occurs within a peripheral module. Some examples of interrupt-capable
events are expiration of a counter within a timer module, receipt of a character in a communications
module, and completion of a conversion in an analog-to-digital converter (ADC) module.
Interrupts are not always generated when an event occurs; the peripheral must make an interrupt request
to the central interrupt manager (CIM) based upon the event occurrence. Typically, the peripheral
contains:
• An interrupt flag bit for each event to signify the event occurrence
• An interrupt-enable bit to control whether the event occurrence causes an interrupt request to the CIM
16.4.3 CIM Interrupt Management (CIM)
A block diagram of the CIM is shown below:
504
Control System Module
Copyright © 2016, Texas Instruments Incorporated
SNIU028A – February 2016 – Revised April 2016
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