Texas Instruments UCD3138 Technical Reference Manual page 28

14-1. ARM Processor Operating Modes
14-2. General-Purpose Registers and Program Counter
14-3. Current Program Status Register
14-4. Bit Patterns in Different ARM Processor Operating Modes
14-5. ARM Processor Exceptions
15-1. ROM and Program Flash Memory Map (ROM Operation)
15-2. Memory Map (Flash Operation)
15-3. RAM and Data Flash Memory Map (ROM and Flash Operation)
15-4. Memory Map (System and Peripherals Blocks)
15-5. Static Memory Control Register (SMCTRL) Register Field Descriptions
15-6. Write Control Register (WCTRL) Register Field Descriptions
15-7. Peripheral Control Register (PCTRL) Register Field Descriptions
15-8. Peripheral Location Register (PLOC) Register Field Descriptions
15-9. Peripheral Protection Register (PPROT) Register Field Descriptions
15-10. Memory Fine Base Address High Register 0 (MFBAHR0) Register Field Descriptions
15-11. Memory Fine Base Address Low Register 0 (MFBALR0) Register Field Descriptions
15-12. Memory Fine Base Address High Register 1-3, 17-19 (MFBAHRx) Register Field Descriptions
15-13. Memory Fine Base Address Low Register 1-3, 17-19 (MFBALRx) Register Field Descriptions
15-14. Memory Fine Base Address High Register 4 (MFBAHR4) Register Field Descriptions
15-15. Memory Fine Base Address Low Register 4-17 (MFBALRx) Register Field Descriptions
15-16. Memory Fine Base Address High Register 5 (MFBAHR5) Register Field Descriptions
15-17. Memory Fine Base Address High Register 6 (MFBAHR6) Register Field Descriptions
15-18. Memory Fine Base Address High Register 7 (MFBAHR7) Register Field Descriptions
15-19. Memory Fine Base Address High Register 8 (MFBAHR8) Register Field Descriptions
15-20. Memory Fine Base Address High Register 9 (MFBAHR9) Register Field Descriptions
15-21. Memory Fine Base Address High Register 10 (MFBAHR10) Register Field Descriptions
15-22. Memory Fine Base Address High Register 11 (MFBAHR11) Register Field Descriptions
15-23. Memory Fine Base Address High Register 12 (MFBAHR12) Register Field Descriptions
15-24. Memory Fine Base Address High Register 13 (MFBAHR13) Register Field Descriptions
15-25. Memory Fine Base Address High Register 14 (MFBAHR14) Register Field Descriptions
15-26. Memory Fine Base Address High Register 15 (MFBAHR15) Register Field Descriptions
15-27. Memory Fine Base Address High Register 16 (MFBAHR16) Register Field Descriptions
15-28. PFLASHCTRL Addresses
15-29. Program Flash Control Register (PFLASHCTRL) Register Field Descriptions
15-30. Data Flash Control Register (DFLASHCTRL) Register Field Descriptions
15-31. Flash Interlock Register (FLASHILOCK) Register Field Descriptions
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16-1.
16-2. Interrupt Priority Table
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16-3.
16-4. Clock Control Register (CLKCNTL) Register Field Descriptions
16-5. System Exception Control Register (SYSECR) Register Field Descriptions
16-6. System Exception Status Register (SYSESR) Register Field Descriptions
16-7. Abort Exception Status Register (ABRTESR) Register Field Descriptions
16-8. Global Status Register (GLBSTAT) Register Field Descriptions
16-9. Device Identification Register (DEV) Register Field Descriptions
16-10. System Software Interrupt Flag Register (SSIF) Register Field Descriptions
16-11. System Software Interrupt Request Register (SSIR) Register Field Descriptions
18-1. IRQ Index Offset Vector Register (IRQIVEC) Register Field Descriptions
18-2. FIQ Index Offset Vector Register (FIQIVEC) Register Field Descriptions
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List of Tables
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Copyright © 2016, Texas Instruments Incorporated
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SNIU028A - February 2016 - Revised April 2016
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