Adc Control Register (Adcctrl) Register Field Descriptions - Texas Instruments UCD3138 Technical Reference Manual

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Table 8-5. ADC Control Register (ADCCTRL) Register Field Descriptions (continued)
Bit Field
19-16 EXT_TRIG_SEL
15-13 SAMPLING_SEL
12 ADC_SEL_REF
11 ADC_ROUND
10-8 BYPASS_EN
7-4 MAX_CONV
3 SINGLE_SWEEP
2 SW_START
1 ADC_INT_EN
0 ADC_EN
SNIU028A – February 2016 – Revised April 2016
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Type Reset
R 0000
Selects which external trigger can start a conversion loop. 0 = HS Loop1 Event 1
(DPWMA Low Resolution Edge) (Default)
1 = HS Loop1 Event 3 (DPWMB Low Resolution Edge)
2 = HS Loop2 Event 1 (DPWMA Low Resolution Edge)
3 = HS Loop2 Event 3 (DPWMB Low Resolution Edge)
4 = HS Loop3 Event 1 (DPWMA Low Resolution Edge)
5 = HS Loop3 Event 3 (DPWMB Low Resolution Edge)
6 = HS Loop4 Event 1 (DPWMA Low Resolution Edge)
7 = HS Loop4 Event 3 (DPWMB Low Resolution Edge)
8 = ADC_EXT_TRIG pin
9 = Analog Comparator A Output
A = Analog Comparator B Output
B = Analog Comparator C Output
C = Analog Comparator D Output
D = Analog Comparator E Output
E = Analog Comparator F Output
F = Analog Comparator G Output
R/W 000
Defines ADC sampling and hold timing setup
111 = 1008KS/s
110 = 267KS/s
101 = 1008KS/s
100 = 538KS/s
011 = 504KS/s
010 = 744KS/s
001 = 744KS/s
000 = 267KS/s (Default)
R/W 0
ADC Voltage Reference Select
0= Selects Internal ADC voltage reference (Default)
1 = Selects AVDD as ADC voltage reference
R/W 0
Enables rounding of ADC Result to 10 bits
0 = ADC Results are not rounded (Default)
1 = ADC Results are rounded to 10 most significant bits
R/W 111
Bypasses the dual sample and hold circuitry, Bit 10 controls ADC Channel 5, Bit 9
controls ADC Channel 3 and Bit 8 controls ADC Channel 1
0 = Enables the Dual Sample and Hold circuitry
1 = Disables the Dual Sample and Hold circuitry (Default)
R/W 0000
Maximum number of conversion done in one conversion loop
0x0 = 1 conversion selection converted in the loop (Default)
0xF = All 16 conversion selections converted in the loop
R/W 0
ADC Conversion Mode
0 = Continuous conversion loop runs (Default)
1 = Single conversion loop run
R/W 0
Firmware ADC Conversion Start, bit will be cleared automatically by hardware at end
of ADC conversion
0 = Conversions not initiated by firmware (Default)
1 = Initiate an ADC conversion loop
R/W 0
End-of-conversion Interrupt Enable
0 = Disable End-of-Conversion Interrupt (Default)
1 = Enable End-of-Conversion Interrupt
R/W 0
ADC12 Enable Control
0 = Disables ADC (Default)
1 = Enables ADC
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Description
ADC12 Overview
ADC Registers
317