2.24 Dpwm Interrupt Register; 2.24.1 Dpwm Period Interrupt Bits; 2.24.2 Mode Switching Interrupt Bits; 2.24.3 Int Bit - Texas Instruments UCD3138 Technical Reference Manual

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2.24 DPWM Interrupt Register

The DPWMINT register has interrupt enable bits, interrupt flags, one interrupt flag clear bit, and one
interrupt scale register.
For more information on the enable bits and flags related to faults, see

2.24.1 DPWM Period Interrupt Bits

There are three bit fields related to the Period interrupt.
PRD is the flag which indicates that there is a period interrupt occurring. It is only a strobed signal, so it is
very unlikely that it will ever be read as set. If the interrupt bit is set, and no other bits are set, this means
it is the period bit which has set it.
PRD_INT_EN enables the period interrupt.
PRD_INT_SCALE programs a divider for the period interrupt. The selections range from an interrupt every
period to an interrupt every 256 periods. See the DPWM Reference section for the table.
Note that if the DPWM is disabled, under most circumstances, it will generate a period interrupt
continuously, if the interrupt is enabled.

2.24.2 Mode Switching Interrupt Bits

There are three bit fields related to the Mode Switching Interrupt.
See Section 2.29 DPWM Auto Switch Registers, for more detail on Mode Switching.
MODE_SWITCH goes high when the DPWM has switched modes.
MODE_SWITCH_INT_EN enables this interrupt.
A rising edge on MODE_SWITCH_FLAG_CLR clears the MODE_SWITCH bit. This bit is not auto cleared,
so it will be necessary to clear it with firmware before the next rising edge.

2.24.3 INT Bit

The INT bit shows that one or more of the interrupt flags is set and enabled, and the DPWM is sending an
interrupt to the Central Interrupt Module (CIM). When the interrupt bits are cleared, so is the INT bit.

2.25 DPWM Counter Preset Register

If enabled, the DPWMCNTPRE register is loaded into the Period Counter at DPWM startup or on a rising
sync edge. This is used for applications requiring complex synchronization and phase shifting between
DPWMs. See 2.16.1 Period Counter Preset Enable for more information.

2.26 Blanking Registers

There are 4 Blanking Registers in each DPWM:
DPWMBLKABEG
DPWMBLKBBEG
DPWMBLKAEND
DPWMBLKBEND
There are two blanking periods, A and B, which both have a beginning and an end, measured in 4
nanosecond steps of the period counter.
These registers are used to blank out CBC signals during noisy times of the signal, for example around
hard switching. See the Fault Mux section for more information. They can also be used to align current
limit response times between multiple DPWMs with different dead times.
The Blank B values are also used to generate the DPWMC signal for the IntraMux for complex topologies.
See Section 2.15.2.
SNIU028A – February 2016 – Revised April 2016
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DPWM Interrupt Register
Section 6.11.
Digital Pulse Width Modulator (DPWM)
65