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Texas Instruments UCD3138 Technical Reference Manual

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Ucd3138 Digital Power Supply Controller Technical Reference Manual
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UCD3138 Digital Power Supply Controller

Technical Reference Manual

Literature Number: SNIU028A

February 2016 – Revised April 2016

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Summary of Contents for Texas Instruments UCD3138

Page 1 UCD3138 Digital Power Supply Controller Technical Reference Manual Literature Number: SNIU028A February 2016 – Revised April 2016...
Page 2: Table Of Contents
Contents ........................Introduction ....................Scope of This Document ......A Guide to Other Documentation for all Members of UCD3138 Family of Products ................. Digital Pulse Width Modulator (DPWM) ..................... DPWM Block Diagram ............. Introduction to DPWM (DPWM Multi-Mode, Open Loop) ......................
Page 3 2.31.18 DPWM Counter Preset Register (DPWMCNTPRE) ............ 2.31.19 DPWM Blanking A Begin Register (DPWMBLKABEG) ............2.31.20 DPWM Blanking A End Register (DPWMBLKAEND) SNIU028A – February 2016 – Revised April 2016 Contents Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 4 3.7.10 Analog Control Register (ACTRL) (For Test Use Only) ............3.7.11 Pre-Bias Control Register 0 (PREBIASCTRL0) ............3.7.12 Pre-Bias Control Register 1 (PREBIASCTRL1) Contents SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 5 4.11.12 Filter KI Coefficient 1 Register (FILTERKICOEF1) ............. 4.11.13 Filter KD Coefficient 0 Register (FILTERKDCOEF0) ............. 4.11.14 Filter KD Coefficient 1 Register (FILTERKDCOEF1) SNIU028A – February 2016 – Revised April 2016 Contents Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 6 5.14.21 Global Enable Register (GLBEN) ............5.14.22 PWM Global Period Register (PWMGLBPRD) ............... 5.14.23 Sync Control Register (SYNCCTRL) ..............5.14.24 Light Load Control Register (LLCTRL) Contents SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 7 6.11.24 DPWM 3 Fault AB Detection Register (DPWM3FLTABDET) ..........6.11.25 DPWM 3 Fault Detection Register (DPWM3FAULTDET) ..............6.11.26 HFO Fail Detect Register (HFOFAILDET) SNIU028A – February 2016 – Revised April 2016 Contents Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 8 8.18.8 ADC Result Registers 0-15 (ADCRESULTx, x=0:15) ........8.18.9 ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15) ........8.18.10 ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5) Contents SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 9 10.3.12 Simple Read with Manual Slave Address ACK ................10.3.13 Write/Read with Repeated Start ..................10.3.14 Automatic PEC Addition ....................10.4 Avoiding Clock Stretching SNIU028A – February 2016 – Revised April 2016 Contents Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 10 11.18 Watchdog Timer Example ................11.19 Warnings for Watchdog Status Register ..................11.20 System Fault Recovery Basics ..................11.21 Timer Module Register Reference Contents SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 11 13.4.1 Write 4 Bytes ....................13.4.2 Write 16 Bytes .................... 13.4.3 Write Next 16 Bytes ......................13.5 Flash Functions ...................... 13.5.1 Mass Erase SNIU028A – February 2016 – Revised April 2016 Contents Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 12 13.6.1 Calculation of Checksum ..................... 13.6.2 Reading Checksum ..................13.7 Trim Flash Checksum Verification ............13.8 Boot ROM for the Other Members of the UCD3138 Family ................13.8.1 UCD3138064 and UCD3138064A ................13.8.2 UCD3138A64 and UCD3138A64A ................13.8.3 UCD3138128 and UCD3138128A ......................
Page 13 17.2.4 3138 Family Members with Multiple Flash Blocks ..............17.3 Flash Management for Firmware Development ..............17.3.1 Best Practice for Firmware Development ..............17.3.2 Firmware Development with "Backdoors" SNIU028A – February 2016 – Revised April 2016 Contents Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 14 FIQ/IRQ Program Control Register (FIRQPR) ..............18.4 Pending Interrupt Read Location Register (INTREQ) .................. 18.5 Interrupt Mask Register (REQMASK) ........................Revision History Contents SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 15 .................... 2-9. DPWM – Leading Edge Mode ..................... 2-10. SyncFET IDE (Normal Mode) ........2-11. Resonant LLC implementation in UCD3138 with Automatic Mode Switching .............. 2-12. Mechanism for Automatic Mode Switching in UCD3138 ..................2-13. UCD3138 Edge-Gen & Intra-Mux ..........................
Page 16 2-49. DPWM Edge PWM Generation Control Register (DPWMEDGEGEN) ........... 2-50. DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) ..............2-51. DPWM BIST Status Register (DPWMBISTSTAT) 3-1. Simplified Block Diagram of Front End in UCD3138 (Front End 2 recommended for Peak Current Mode ........................Control) ..........................3-2................
Page 17 Analog Comparator Control 0 Register (ACOMPCTRL0) ............6-6. Analog Comparator Control 1 Register (ACOMPCTRL1) ............6-7. Analog Comparator Control 2 Register (ACOMPCTRL2) SNIU028A – February 2016 – Revised April 2016 List of Figures Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 18 8-10. UCS3138 Digital Comparators Control Block Diagram ..............8-11. Temp Sensor Control Register (TEMPSENCTRL) ................8-12. PMBus Control Register 3 (PMBCTRL3) List of Figures SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 19 10-12. Simple Read of 5 Bytes with Full Automation ..............10-13. Slave Address Manual ACK on a Read Address ..................10-14. Write/Read with Repeated Start SNIU028A – February 2016 – Revised April 2016 List of Figures Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 20 10-59. PMBus Control Register 2 (PMBCTRL2) ..............10-60. PMBus Hold Slave Address Register (PMBHSA) ................10-61. PMBus Control Register 3 (PMBCTRL3) ..........................11-1..........................11-2. List of Figures SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 21 12-11. UART Receive Buffer (UARTRXBUF) ................. 12-12. UART Transmit Buffer (UARTTXBUF) ...... 12-13. UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX) ............. 13-1. UCD3138 Boot ROM Execution After Power-On/Reset ......................... 13-2. Boot Flash ............13-3. UCD3138064 Boot ROM Execution After Power-on/Reset ............
Page 22 18-3. FIQ/IRQ Program Control Register (FIRQPR) ..............18-4. Pending Interrupt Read Location Register (INTREQ) .................. 18-5. Interrupt Mask Register (REQMASK) List of Figures SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 23 List of Tables ............... 2-1. DPWM Register Time Resolutions in UCD3138 ..2-2. DPWM Period Register (DPWMPRD) All other 4 ns registers with standard alignment are the same............. 2-3. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1) 2-4. DPWM Event 2 Register (DPWMEV2) Event 3 and 4 are the same, Cycle Adjust registers only go to bit 15 ........................
Page 24 ........5-8. Filter KComp A Register (FILTERKCOMPA) Register Field Descriptions ........5-9. Filter KComp B Register (FILTERKCOMPB) Register Field Descriptions List of Tables SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 25 6-26. HFO Fail Detect Register (HFOFAILDET) Register Field Descriptions ..........6-27. LFO Fail Detect Register (LFOFAILDET) Register Field Descriptions ............6-28. IDE Control Register (IDECTRL) Register Field Descriptions SNIU028A – February 2016 – Revised April 2016 List of Tables Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 26 ..........9-19. Global I/O Value Register (GLBIOVAL) Register Field Descriptions ..........9-20. Global I/O Read Register (GLBIOREAD) Register Field Descriptions List of Tables SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 27 12-12. UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX) Register Field ....................... Descriptions ............. 13-1. ROM Version for the Other Members of the UCD3138 Family ............... 13-2. Boot ROM Mass Erase Data Byte Parameter Values ............13-3. Boot ROM Execute Flash Command Byte, Valid Values ............
Page 28 18-1. IRQ Index Offset Vector Register (IRQIVEC) Register Field Descriptions ........18-2. FIQ Index Offset Vector Register (FIQIVEC) Register Field Descriptions List of Tables SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 29 ......18-4. Pending Interrupt Read Location Register (INTREQ) Register Field Descriptions ..........18-5. Interrupt Mask Register (REQMASK) Register Field Descriptions SNIU028A – February 2016 – Revised April 2016 List of Tables Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 30: Introduction
267ksps general purpose ADC with up to 14 channels, timers, interrupt control, JTAG debug and PMBus & UART communications ports. In terms of memory, UCD3138 offers 32KB of program flash, 2kB of data flash, 4KB RAM and 4KB of ROM.
Page 31 A Guide to Other Documentation for all Members of UCD3138 Family of Products www.ti.com UCD3138A64/ UCD3138064 UCD3138A Programmer’s UCD3138128 Module Function\Manual Programmer's Programmer's Manual Programmer’s Manual Manual Manual CPCC, DTC, GLBEN, Light load, Loop Mux SLUU995 Analog Comp, Digital Comp, IDE,...
Page 32 ADC, which will trigger the Filter at the end of its conversion. The UCD3138 device supports multiple sets of the Digital Power Peripherals affording the ability to control upto 3 feedback loops (voltage or current) and drive 8 outputs simultaneously. To inter-connect all the DPPs, there is a large module called the Loop Mux.
Page 33: Digital Pulse Width Modulator (Dpwm)
SYNC pin as either an input or an output. In addition, it interfaces to several fault detection circuits. The response to these faults is part of the DPWM function. SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 34 2.29 DPWM Auto Switch Registers ..............2.30 DPWM Edge PWM Generation Register ................2.31 DPWM 0-3 Registers Reference Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 35: Dpwm Block Diagram
Timing Module illustrating the data, signals and main elements involved (once again, the real logic of the Timing Module is not illustrated here). SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 36: Block Diagram Of Timing Module In The Dpwm Module
DPWM Block Diagram www.ti.com Figure 2-2. Block Diagram of Timing Module in the DPWM module Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 37: Introduction To Dpwm (Dpwm Multi-Mode, Open Loop)
In other words, the power supply control loop is not closed. This mode is used for introducing the DPWM because there is a very simple correlation between DPWM register values and signal timing. SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 38: Dpwm Mode - Multi-Mode, Open Loop
Note that Sample Trigger 1 and 2, Blanking A and B, and Phase Trigger are shown at logical locations for this specific mode, but they can be placed anywhere within the period. Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 39: Dpwm Normal Mode
Figure 2-4. DPWM - Normal Mode SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 40 If this is not done, the DPWMB on time may overlap the DPWMA on time, causing shoot through Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 41: Dpwm Phase Shift Mode
DPWM1 Phase Trigger Phase Trigger = Phase Trigger Register value or Filter Duty Figure 2-5. DPWM - Phase Shift Mode SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 42: Dpwm Multiple Output Mode (Multi Mode)
Here is a diagram for Multi mode: Figure 2-6. DPWM – Multiple Output Mode (Multi Mode) Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 43: Dpwm Resonant Mode
The equations for this mode are designed for a smooth transition from PWM mode to Resonant mode, as described in Section 2.10.1. Here is a diagram of this mode: SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 44: Dpwm - Resonant Mode
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End Figure 2-7. DPWM – Resonant Mode Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 45: Triangular Mode
Triangular Mode, only DPWM B is available. Here is a diagram for Triangular Mode: Figure 2-8. DPWM – Triangular Mode SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 46: Dpwm Leading Edge Mode
DPWMA rising edge by a fixed dead time. Here is a diagram of the Leading Edge Mode: Figure 2-9. DPWM – Leading Edge Mode Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 47: Sync Fet Ramp And Ide Calculation
However, in discontinuous mode, the SR FET needs to be turned off before the end of the period. The UCD3138 hardware provides an automatic function to make this easier. In this case, the falling edge of DPWMB is adjusted, as shown below:...
Page 48: 2.10 Automatic Mode Switching
> fr Tr = 1/fr Tr = 1/fr Figure 2-11. Resonant LLC implementation in UCD3138 with Automatic Mode Switching 2.10.2 Mechanism for Automatic Mode Switching Many of the configuration parameters for the DPWM, including the mode, are in DPWM Control Register 1.
Page 49: Mechanism For Automatic Mode Switching In Ucd3138
Control Register 1 Figure 2-12. Mechanism for Automatic Mode Switching in UCD3138 As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Control Register 1 until the Low Lower Threshold is passed.
Page 50: 2.11 Dpwmc, Edge Generation, Intramax
2.11 DPWMC, Edge Generation, IntraMax The UCD3138 has sophisticated hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed. The DPWMC, the Edge Generation Module, and the IntraMux play a key role in delivering this capability.
Page 51: 2.12 Time Resolution Of Various Dpwm Registers
Different registers in the DPWM block have different time resolutions. Pulse widths are generally adjustable in nominal 250 picosecond steps, while period and phase shift are adjustable in 4 nanosecond steps. The sample trigger is adjustable in 16 nanosecond steps. Table 2-1. DPWM Register Time Resolutions in UCD3138 Register Resolution...
Page 52: Dpwm Period Register (Dpwmprd) All Other 4 Ns Registers With Standard Alignment Are The Same
4 ns LSbit 14 (unsigned) On the UCD3138, all these registers are aligned so that their bit fields match the scaling, except for the Resonant Duty and Adaptive Sample register. All the registers are unsigned, except for the 2 adjust registers, Resonant Duty and Adaptive Sample register, which are signed to permit positive or negative adjustment.
Page 53: 2.13 Pwm Counter And Clocks
DPWMB pins. For details of the Intra Mux, see Section 2.11. These fields also occur in the AMS registers. SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 54: 2.15.3 Cycle By Cycle Current Limit Enable
With a positive dead time, of course, DPWMA will fall with the CBC event, and DPWMB will rise after the dead time: Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 55: Truth Table
Table 2-5. Truth Table CBC_PWM_AB_EN CBC_ADV_CNT_EN CBC_BSIDE_ACTIVE_EN CBC A CBC B Duty Match B matches A both match SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 56: 2.15.4 Multi Mode On/Off
These bits are not duplicated in the AMS registers. These two graphs show modes 1 and 2 with PMMINDUTYLOW at 30, and DPWMMINDUTYHI at 70. Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 57: Minimum Duty Mode
Min duty mode 2 with hysteresis Duty on way down duty on way up Filter duty Figure 2-16. Minimum Duty Mode 2 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 58: 2.15.6 Master Sync Control Select
These bits do not affect the DPWM status after device reset. After reset, all DPWM pins are configured as outputs and actively driven low. These bits are not duplicated in the AMS registers. Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 59: 2.15.11 Blank Enable
2. Sync Received (slave mode enabled) – Period Counter set to preset value 3. Counter reaches Period Register value – Period counter set to zero SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 60: 2.16.2 Sync Fet Ramp Enable
Setting the CLA_DUTY_ADJ_EN bit enables the Current Balancing logic to modify the input to the DPWM so that current controlled by this DPWM can be balanced with the current controlled by another DPWM in the same UCD3138. For more information, see the Current Balancing section.
Page 61: 2.16.10 1.16.10 Event Update Select
For most topologies, mode 1 is used, and dead times or minimum pulse widths are used to keep moving edges out of the first 72nsec of the DPWM period. Please refer to the reference firmware code provided with UCD3138 EVMs for specific guidance regarding each topology. 2.16.11 Check Override The CHECK_OVERRIDE bit, when set, overrides the internal DPWM checking.
Page 62: 2.16.14 High Resolution Enable/Disable
2.16.15 Asynchronous Protection Disable The PWM_A_PROT_DIS and PWM_B_PROT_DIS bits disable asynchronous protection on their respective pins. Please consult to the reference firmware code provided with UCD3138 EVMs for specific guidance on whether to set these bits or not in the desired topology.
Page 63: 2.17.3 Filter Duty Select
Sample Trigger Register – 16 nanoseconds. The adaptive register, though is not mapped the same. Bit 0 is the first usable bit. See Section 2.31 for more information. SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 64: 2.17.7 Sample Trigger Enable Bits
DPWM pins when they are used as general purpose I/O. It also has 6 bits which indicate that the protection logic for the DPWM has detected overflows. Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 65: 2.24 Dpwm Interrupt Register
The Blank B values are also used to generate the DPWMC signal for the IntraMux for complex topologies. Section 2.15.2. SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 66: 2.27 Dpwm Adaptive Sample Register
Address 00070000 – DPWM 2 Control Register 0 Address 000A0000 – DPWM 1 Control Register 0 Address 000D0000 – DPWM 0 Control Register 0 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 67: Dpwm Control Register 0 (Dpwmctrl0)
0 = PWM A pulse width controlled by Filter Calculation (Default) 1 = PWM A pulse width controlled by Event1 and Event2 registers SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 68 0 = Normal Mode 1 = Resonant Mode 2 = Multi-Output Mode (Default) 3 = Triangular Mode 4 = Leading Mode Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 69 1 = Enable CLA input (Default) PWM_EN PWM Processing Enable 0 = Disable PWM module, outputs zero (Default) 1 = Enable PWM operation SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 70: Dpwm Control Register 1 (Dpwmctrl1)
0010 = Sync Out generated once every 3 switching cycles ………. 1111 = Sync Out generated once every 16 switching cycles Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 71: Dpwm Control Register 1 (Dpwmctrl1) Register Field Descriptions
Enables GPIO mode for PWM A output 0 = PWM A in DPWM mode (Default) 1 = PWM A in GPIO mode SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 72: Dpwm Control Register 1 (Dpwmctrl1)
HIRES_DIS PWM High Resolution Disable 0 = Enable High Resolution logic (Default) 1 = Disable High Resolution logic Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 73: Dpwm Control Register 2 (Dpwmctrl2)
11 = Trigger value is adaptive midpoint (EV1+CLA_DUTY + Fixed offset + Adaptive Offset) and uses current CLA value at update event SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 74: Dpwm Control Register 2 (Dpwmctrl2)
SAMPLE_TRIG_1 Sample Trigger 1 Enable 0 = Disable Sample Trigger 1 1 = Enable Sample Trigger 1 (Default) Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 75: Dpwm Period Register (Dpwmprd)
Reset Description 17-4 00 0011 PWM Period. Low resolution register, last 4 bits are read-only. 0100 0001 Reserved SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 76: Dpwm Event 1 Register (Dpwmev1)
00 0000 Configures the location of Event 1. Low resolution register, last 4 bits are unused. 0001 0100 Reserved Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 77: Dpwm Event 2 Register (Dpwmev2)
Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0 (dependent 0000 on Bits 3:2 of DPWM Control Register 2). 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 78: Dpwm Event 3 Register (Dpwmev3)
Configures the location of Event 3. Value equals number of PCLK clock periods in 0011 Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0. 1110 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 79: Dpwm Event 4 Register (Dpwmev4)
Configures the location of Event 4. Value equals number of PCLK clock periods in 0111 Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0. 0000 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 80: Dpwm Sample Trigger 1 Register (Dpwmsamptrig1)
PCLK clock periods. Enables start of conversion for EADC. Low resolution 0000 register, last 6 bits are read-only. Reserved 00 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 81: Dpwm Sample Trigger 2 Register (Dpwmsamptrig2)
PCLK clock periods. Enables start of conversion for EADC. Low resolution 0000 register, last 6 bits are read-only. Reserved 00 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 82: Dpwm Phase Trigger Register (Dpwmphasetrig)
Configures the phase trigger delay within multi-output mode. Value equals the 0000 number of PCLK clock periods. Low resolution register, last 4 bits are read-only. 0000 Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 83: Dpwm Cycle Adjust A Register (Dpwmcycadja)
Adjusts PWM A output signal. 16-bit signed number allows output signal to be 0000 delayed or sped up. 0000 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 84: Dpwm Cycle Adjust B Register (Dpwmcycadjb)
Adjusts the PWM B output signal. 16-bit signed number allows output signal to be 0000 delayed or sped up. 0000 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 85: Dpwm Resonant Duty Register (Dpwmresduty)
Controls the DPWM duty. 16-bit signed number is used as a Filter Output Multiplier _DUTY 0000 in Resonant Mode. 0000 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 86: Dpwm Fault Control Register (Dpwmfltctrl)
Fault B Count, sets the number of received sequential faults on Fault B input before asserting the fault Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 87: Dpwm Overflow Register (Dpwmoverflow)
OVERFLOW[0] – CLA Event 2 Overflow Status 0 = CLA Event 2 has not overflowed 1 = Overflow condition found on CLA Event 2 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 88: Dpwm Interrupt Register (Dpwmint)
1 = Risedge 0-1 clears flag generated. MODE_SWITCH_ Mode Switching Flag Clear FLAG_EN 0 = (Default) 1 = Risedge 0-1 clears flag generated. Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 89 1110 = Period Interrupt generated once every 224 switching cycles 1111 = Period Interrupt generated once every 256 switching cycles SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 90: Dpwm Counter Preset Register (Dpwmcntpre)
0000 PRESET_EN bit in DPWMCTRL2 is enabled. Low resolution register, last 4 bits are 0000 read-only. Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 91: Dpwm Blanking A Begin Register (Dpwmblkabeg)
Configures start of Comparator Blanking Window for PWM A. Low resolution register, 0000 last 4 bits are read-only. 0000 Reserved 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 92: Dpwm Blanking A End Register (Dpwmblkaend)
Configures end of Comparator Blanking Window for PWM A. Low resolution register, 0000 last 4 bits are read-only. 0000 Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 93: Dpwm Blanking B Begin Register (Dpwmblkbbeg)
Configures start of Comparator Blanking Window for PWM B. Low resolution register, 0000 last 4 bits are read-only. 0000 Reserved 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 94: Dpwm Blanking B End Register (Dpwmblkbend)
Configures end of Comparator Blanking Window for PWM B. Low resolution register, 0000 last 4 bits are read-only. 0000 Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 95: Dpwm Minimum Duty Cycle High Register (Dpwmmindutyhi)
Configures upper threshold for minimum duty cycle logic. Low resolution register, last 0000 4 bits are read-only. 0000 Reserved 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 96: Dpwm Minimum Duty Cycle Low Register (Dpwmmindutylo)
Configures lower threshold for minimum duty cycle logic. Low resolution register, last 0000 4 bits are read-only. 0000 Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 97: Dpwm Adaptive Sample Register (Dpwmadaptive)
Table 2-30. DPWM Adaptive Sample Register (DPWMADAPTIVE) Register Field Descriptions Field Type Reset Description 11-0 ADAPT_SAMP 0000 Configures Adaptive Sample Adjust 0000 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 98: Dpwm Fault Status (Dpwmfltstat)
Current Limit Detection Status 0 = Current Limit Detection is not asserted 1 = Current Limit Detection is set Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 99: Dpwm Auto Switch High Upper Thresh Register (Dpwmautoswhiupthresh)
Auto Switch High Upper and Auto Switch High Lower 0000 thresholds. Low resolution register, last 4 bits are read-only. Reserved 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 100: Dpwm Auto Switch High Lower Thresh Register (Dpwmautoswhilowthresh)
Auto Switch High Upper and Auto Switch High Lower 0000 thresholds. Low resolution register, last 4 bits are read-only. Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 101: Dpwm Auto Switch Low Upper Thresh Register (Dpwmautoswloupthresh)
Auto Switch Low Upper and Auto Switch Low Lower 0000 thresholds. Low resolution register, last 4 bits are read-only. Reserved 0000 SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 102: Dpwm Auto Switch Low Lower Thresh Register (Dpwmautoswlolowthresh)
Auto Switch Low Upper and Auto Switch Low Lower 0000 thresholds. Low resolution register, last 4 bits are read-only. Reserved 0000 Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 103: Dpwm Auto Config Max Register (Dpwmautomax)
Sets if Fault CBC changes output waveform for PWM-C 0 = PWM-C unaffected by Fault CBC (Default) 1 = PWM-C affected by Fault CBC SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 104 CLA Processing Enable 0 = Generate PWM waveforms from PWM Register values (Default) 1 = Enable CLA input Reserved Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 105: Dpwm Auto Config Mid Register (Dpwmautomid)
Sets if Fault CBC changes output waveform for PWM-C 0 = PWM-C unaffected by Fault CBC (Default) 1 = PWM-C affected by Fault CBC SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 106 CLA Processing Enable 0 = Generate PWM waveforms from PWM Register values 1 = Enable CLA input (Default) Reserved Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 107: Dpwm Edge Pwm Generation Control Register (Dpwmedgegen)
5 = Below (n+1) DPWM negedge A 6 = Below (n+1) DPWM posedge B 7 = Below (n+1) DPWM negedge B Reserved SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 108 5 = Below (n+1) DPWM negedge A 6 = Below (n+1) DPWM posedge B 7 = Below (n+1) DPWM negedge B Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 109: Dpwm Filter Duty Read Register (Dpwmfilterdutyread)
Table 2-39. DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) Register Field Descriptions Field Type Reset Description 17-0 FILTER_DUTY Filter Duty value received by DPWM Module SNIU028A – February 2016 – Revised April 2016 Digital Pulse Width Modulator (DPWM) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 110: Dpwm Bist Status Register (Dpwmbiststat)
Table 2-40. DPWM BIST Status Register (DPWMBISTSTAT) Register Field Descriptions Field Type Reset Description 14-0 BIST_CNT BIST Count accumulated during BIST test Digital Pulse Width Modulator (DPWM) SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 111: Front End
(Front End 2 recommended for Peak Current Mode Control) The input to the Front End is a differential signal on 2 input pins (EANx, EAPx, x=0, 1, 2) of the UCD3138 device. A differential amplifier resolves this to a single ended signal, representing the difference between the two pins.
Page 112 There is also a single ended comparator connected with EAP pin and the DAC which is used for Peak Current Mode control. Front End 2 is recommended for Peak Current mode control because blanking time is available only on FE2 in UCD3138(RMH,RHA,RGC). All of these are described in more details in later sections of this chapter.
Page 113: Error Adc And Front End Gain
3 - 8 +124 to -128 2 - 7 +62 to -64 1 - 6 +31 to -32 0 - 5 SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 114 It is also sent to the Filter, and is one of the values which can be used by the digital comparators controlled by the Fault Mux. Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 115: Eadc Triggering, Eadc Output To Filter
There is a bit which initializes the state machine counter for the front end to a non-zero value. This should be left at 0, however. Other numbers will cause unexpected results. FeCtrl0Regs.EADCCTRL.bit.SCFE_CNT_INIT = 0; //leave at 0. SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 116: Eadc Averaging
This value will reflect the averaging value if averaging is enabled. Otherwise it will be the same as the raw EADC value mentioned earlier. Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 117 For a simultaneous startup, it is necessary to set the local bits before writing to the global register. SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 118: Enabling Eadc And Front End 3.2 Front End Dac
Note that if the DPWM pin is not active, because of anything from a zero filter output to a fault, the dither counter will not be incremented. To enable dither, the DAC_DITHER_EN bit must be set: FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = (int)(100.25 * 16); Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 119: Ramp Module
3 ramp functions running simultaneously. 3.3.1 DAC Ramp Overview The Front End Control Module in UCD3138 provides the capability to generate an automated ramp of the DAC set point through hardware. Firmware has the capability to configure the following parameters of the ramp: 1.
Page 120: Dac Ramp Steps
Every step, 0x100 would be added to the step register. The sequence would look like this: Table 3-2. Hidden Step Register DAC Register 0x000100 0x0000 0x000200 0x0000 0x000300 0x0000 0x000400 0x0001 Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 121: Dac Ramp Start, Interrupts, Start Delay
For additional information consult the reference firmware provided with UCD3138PSFBEVM-029 EVM and TI application note on Phase Shift Full Bridge (Peak Current mode control) implementation. SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 122: Sync Fet Soft On/Off Using Ramp Module
These two modules control the width of DPWMB as shown below: Figure 3-8. Ideal Diode Emulation (IDE) Module in UCD3138 The Sync FET Ramp is similar to the DAC Ramp, and uses the same hardware, but it needs a starting point, which is provided by the SYNC_FET_RAMP_START bits in the RAMPCTRL register.
Page 123: Successive Approximation Mode
EADC error, the AFE gain and DAC setpoint are adjusted. 3.4.3 Non-Continuous SAR Mode UCD3138 features two modes when it attempts to use a SAR algorithm to determine an absolute voltage. The first mode is Non-Continuous SAR mode. In this mode, the SAR Control Module restarts the SAR algorithm on each sample trigger from the DPWM module.
Page 124: Absolute Value Without Sar
Provides the starting value for the SyncFET Ramp with a resolution of High _RAMP_START 0000 Frequency Oscillator Period/bit 0000 15-13 Reserved Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 125 0 = No soft start or power-down ramp controlled by hardware (Default) 1 = Enables hardware control of soft start or power-down ramp SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 126: Ramp Status Register (Rampstat)
1 = Ramp delay procedure is complete PREBIAS Pre-Bias Complete, Raw Status _STATUS 0 = Pre-Bias is not completed 1 = Pre-Bias is completed Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 127: Ramp Cycle Register (Rampcycle)
0 = 1 switching cycle per step (Default) 1 = 2 subcycles per cycle 2 = 3 subcycles per cycle ……. 127 = 128 subcycles per cycle SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 128: Eadc Dac Value Register (Eadcdac)
0 = DAC Dithering disabled (Default) 1 = DAC Dithering enabled Reserved 13-0 DAC_VALUE 00 1111 Programmable DAC Value, effective LSB equals 0.09765625mV 1111 0000 Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 129: Ramp Dac Ending Value Register (Rampdacend)
Table 3-7. Ramp DAC Ending Value Register (RAMPDACEND) Register Field Descriptions Field Type Reset Description 13-0 RAMP_DAC 00 0000 Programmable Ramp Ending DAC Value, LSB equals 0.09765625mV _VALUE 0000 0000 SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 130: Dac Step Register (Dacstep)
DAC Step (0-255 DAC counts at bit resolution of 0.09765625mV). Bits 9:0 represent 0000 the fractional portion of the DAC Step. 0000 Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 131: Dac Saturation Step Register (Dacsatstep)
1 = DAC adjusted by 1 DAC count on EADC saturation during ramp ….. 1023 = DAC adjusted by 1023 DAC counts on EADC saturation during ramp SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 132: Eadc Trim Register (Eadctrim) - (For Factory Test Use Only)
01 1000 Sets trim for 1X AFE Gain. Register will be programmed during test and should not be overwritten by firmware. Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 133: Eadc Control Register (Eadcctrl)
Enables EADC Data Inversion on data to filter module 0 = EADC Data is not inverted (Default) 1 = EADC Data Inverted SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 134 1 = Enables Switch Cap Front End logic (Default) EADC_ENA EADC Enable 0 = Disables EADC 1 = Enables EADC (Default) Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 135: Analog Control Register (Actrl) (For Test Use Only)
1 = Selects External V_SE, bypass EADC ANALOG_ENA Analog Front End Enable 0 = Disables Analog Front End 1 = Enables Analog Front End (Default) SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 136: Pre-Bias Control Register 0 (Prebiasctrl0)
0 to 255. If PREBIAS_STATUS is set, it will take PRE_BIAS_LIMIT samples outside of acceptable range before clearing PREBIAS_STATUS. Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 137: Pre-Bias Control Register 1 (Prebiasctrl1)
255 = DAC Setpoint adjustment after 256 EADC samples 15-14 Reserved 13-0 MAX_DAC_ADJ 00 0000 Configures the maximum DAC setpoint adjustment step 0000 0000 SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 138: Sar Control Register (Sarctrl)
1 = 4mV Resolution, 2x AFE Gain 2 = 2mV Resolution, 4x AFE Gain 3 = 1mV Resolution, 8x AFE Gain Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 139: Sar Timing Register (Sartiming)
Configures timing for Bits 7:6 of DAC setpoint for SAR Algorithm Reserved SAR_TIMING Configures timing for Bits 5:0 of DAC setpoint for SAR Algorithm _LOWER SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 140: Eadc Value Register (Eadcvalue)
1 = EADC output is saturated at low limit 13-9 Reserved 00 000 ERROR_VALUE Signed 9-bit Error value measured by Front End Control Module with a resolution of 1mV/bit Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 141: Eadc Raw Value Register (Eadcrawvalue)
Signed 9-bit Error value measured by Front End Control Module with a resolution of _VALUE 1mV/bit. Value is raw EADC data before averaging. SNIU028A – February 2016 – Revised April 2016 Front End Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 142: Dac Status Register (Dacstat)
Table 3-19. DAC Status Register (DACSTAT) Register Field Descriptions Field Type Reset Description DAC_VALUE 00 0000 Current 10-bit Value sent to DAC 0000 Front End SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 143: Filter
Chapter 4 SNIU028A – February 2016 – Revised April 2016 Filter The UCD3138 filter is a PID filter with many enhancements for power supply control. Some of its features include: • PID Based Architecture • Additional α coefficient and history in D branch •...
Page 144: Filter Math Details
7 different coefficient sets selected by the Xn value. This can be used to change the compensation of the filter with different input error ranges. For a complete discussion of this feature, see Section 4.3.6. Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 145: Proportional Branch
There is also a simple clamp to prevent the K output from going outside a 24 bit signed number. Because of the integral element for the alpha stage, it is possible for it to exceed this range. SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 146: Add, Saturate, Scale And Clamp
24 bits, or results may be unexpected. Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 147: Filter Output Stage
18 bit result are truncated. The Filter Period only presents the high 14 bits to the DPWM, giving a resolution of a nominal 4 nanoseconds. SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 148: Filter Status Register
Filter sources and destinations are set in the Loop Mux registers KI_ADDER_MODE PERIOD_MULT_SEL OUTPUT_MULT_SEL YN_SCALE NL_MODE KD_STALL KI_STALL KP_OFF KD_OFF KI_OFF FORCE_START USE_CPU_SAMPLE F ILTER_EN Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 149: Filter Enable
2, -1 means shift left by 1, and so on. Filter1Regs.FILTERCTRL.bit.OUTPUT_SCALE = -3; //shift filter output left by 3 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 150: Output Multiplier Select
Here is an example of its use: LoopMuxRegs.FILTERMUX.bit.FILTER0_PER_SEL = 2; //use DPWM2 period for filter 0 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 151: Kcomp As Output Multiplier
Configuring the link between the two filters is simple and is shown below. The actual filter settings and operation for feed forward are available in the Hard Switching Full Bridge EVM (UCD3138HSFBEVM-029) reference code from Texas Instruments. Here is an example of link code: LoopMuxRegs.FILTERMUX.bit.FILTER0_FFWD_SEL = 0;...
Page 152: Xn, Yn Read And Write Registers
The proportional output is not provided. It can be determined by multiplying Xn by KP, or by subtracting KiYn and KdYn from Yn. Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 153: Coefficient Configuration Register
These bins are selected based on the nonlinear limit register contents and the Xn value into the filter. There are two options – symmetrical and non-symmetrical. Here are the bins for the two modes: SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 154 Filter0Regs.COEFCONFIG.bit.BIN2_ALPHA = 0; //alpha 0 Filter0Regs.COEFCONFIG.bit.BIN3_ALPHA = 0; //alpha 0 Filter0Regs.COEFCONFIG.bit.BIN4_ALPHA = 1; //alpha 1 Filter0Regs.COEFCONFIG.bit.BIN5_ALPHA = 1; //alpha 1 Filter0Regs.COEFCONFIG.bit.BIN6_ALPHA = 1; //alpha 1 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 155: Kp, Ki, And Kd Registers
Here is a code example loading them for symmetric mode: Filter1Regs.FILTERNL2.bit.LIMIT5 = 218; //symmetric values Filter1Regs.FILTERNL2.bit.LIMIT4 = 182; Filter1Regs.FILTERNL1.bit.LIMIT3 = 145; Filter1Regs.FILTERNL1.bit.LIMIT2 = 109; Filter1Regs.FILTERNL0.bit.LIMIT1 = 72; Filter1Regs.FILTERNL0.bit.LIMIT0 = 36; SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 156: Filter Status Register (Filterstatus)
Figure 4-6. Filter Status Register (FILTERSTATUS) FILTER_BUSY YN_LOW_CLAMP YN_HIGH_CLAMP KI_YN_LOW_CLAMP KI_YN_HIGH_CLAMP LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 157: Filter Status Register (Filterstatus) Register Field Descriptions
KI Feedback High Rail Indicator 0 = KI Feedback not equal to high rail 1 = KI Feedback equal to high rail SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 158: Filter Control Register (Filterctrl)
Freezes KI Branch, KI_YN remains at current value 0 = KI_YN recalculated on each filter update (Default) 1 = KI_YN stalled at present value Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 159 1 = CPU Mode, input data based on CPU XN register FILTER_EN Filter Enable 0 = Disables Filter operation 1 = Enables Filter operation (Default) SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 160: Cpu Xn Register (Cpuxn)
Forced Xn value, allows processor to use filter as ALU. Set Bit 2 of Filter Control 0000 Register to ‘1’ to force CPU_SAMPLE as input to Filter. Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 161: Filter Xn Read Register (Filterxnread)
Field Type Reset Description 24-16 XN_M1 9-bit signed XN_M1 register value, read-only 15-9 Reserved 000 0000 9-bit signed XN register value, read-only SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 162: Filter Ki_Yn Read Register (Filterkiynread)
Table 4-5. Filter KI_YN Read Register (FILTERKIYNREAD) Register Field Descriptions Field Type Reset Description 23-0 KI_YN 24-bit signed KI_YN register value, read-only Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 163: Filter Kd_Yn Read Register (Filterkdynread)
Table 4-6. Filter KD_YN Read Register (FILTERKDYNREAD) Register Field Descriptions Field Type Reset Description 23-0 KD_YN 24-bit signed KD_YN register value, read-only SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 164: Filter Yn Read Register (Filterynread)
Table 4-7. 9.7 Filter YN Read Register (FILTERYNREAD) Register Field Descriptions Field Type Reset Description 23-0 24-bit signed YN register value, read-only Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 165: Coefficient Configuration Register (Coefconfig) Register Field Descriptions
EADC sample 0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default) 1 = Bank 1 KD Alpha (KD_ALPHA_1) selected SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 166 EADC sample 0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default) 1 = Bank 1 KD Alpha (KD_ALPHA_1) selected Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 167: Coefficient Configuration Register (Coefconfig)
3 = Coefficient Set D Selected 4 = Coefficient Set E Selected 5 = Coefficient Set F Selected 6 = Coefficient Set G Selected SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 168: Filter Kp Coefficient 0 Register (Filterkpcoef0)
0000 15-0 KP_COEF_0 0100 KP Coefficient 0, 16-bit signed coefficient, configurable to any bin using the 0010 Coefficient Control Register 0011 0100 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 169: Filter Kp Coefficient 1 Register (Filterkpcoef1)
Description 15-0 KP_COEF_2 0000 KP Coefficient 2, 16-bit signed coefficient, configurable to any bin using the 0000 Coefficient Control Register 0000 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 170: Filter Ki Coefficient 0 Register (Filterkicoef0)
0000 15-0 KI_COEF_0 0010 KI Coefficient 0, 16-bit signed coefficient, configurable to any bin using the 0100 Coefficient Control Register 0001 0010 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 171: Filter Ki Coefficient 1 Register (Filterkicoef1)
0000 15-0 KI_COEF_2 0000 KI Coefficient 2, 16-bit signed coefficient, configurable to any bin using the 0000 Coefficient Control Register 0000 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 172: Filter Kd Coefficient 0 Register (Filterkdcoef0)
0000 15-0 KD_COEF_0 1100 KD Coefficient 0, 16-bit signed coefficient, configurable to any bin using the 0100 Coefficient Control Register 0000 0001 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 173: Filter Kd Coefficient 1 Register (Filterkdcoef1)
Description 15-0 KD_COEF_2 0000 KD Coefficient 2, 16-bit signed coefficient, configurable to any bin using the 0000 Coefficient Control Register 0000 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 174: Filter Kd Alpha Register (Filterkdalpha)
15-9 Reserved KD_ALPHA_0 0 0101 Bank 0 KD Alpha, 9-bit signed value, configurable to any bin using the Coefficient 0010 Control Register Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 175: Filter Nonlinear Limit Register 0 (Filternl0)
LIMIT1 0 0000 Configures LIMIT1 in Nonlinear Coefficient tables 0000 15-9 Reserved LIMIT0 0 0000 Configures LIMIT0 in Nonlinear Coefficient tables 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 176: Filter Nonlinear Limit Register 1 (Filternl1)
LIMIT3 0 0000 Configures LIMIT3 in Nonlinear Coefficient tables 0000 15-9 Reserved LIMIT2 0 0000 Configures LIMIT2 in Nonlinear Coefficient tables 0000 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 177: Filter Nonlinear Limit Register 2 (Filternl2)
LIMIT5 0 0000 Configures LIMIT5 in Nonlinear Coefficient tables 0000 15-9 Reserved LIMIT4 0 0000 Configures LIMIT4 in Nonlinear Coefficient tables 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 178: Filter Ki Feedback Clamp High Register (Filterkiclphi)
Sets the upper limit of KI_YN value. If calculated KI_YN exceeds this threshold, the 1111 KI_YN register will be set to KI_CLAMP_HIGH 1111 1111 1111 1111 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 179: Filter Ki Feedback Clamp Low Register (Filterkiclplo)
Sets the lower limit of KI_YN value. If calculated KI_YN falls below this threshold, the 0000 KI_YN register will be set to KI_CLAMP_LOW 0000 0000 0000 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 180: Filter Yn Clamp High Register (Filterynclphi)
Sets the upper limit of YN value. If calculated YN exceeds this threshold, the YN 1111 register will be set to YN_CLAMP_HIGH 1111 1111 1111 1111 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 181: Filter Yn Clamp Low Register (Filterynclplo)
Sets the lower limit of YN value. If calculated YN falls below this threshold, the YN 0000 register will be set to YN_CLAMP_LOW 0000 0000 0000 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 182: Filter Output Clamp High Register (Filteroclphi)
Sets the upper limit of filter output value. If calculated filter output exceeds this _HIGH 1111 threshold, the filter output will be set to OUTPUT_CLAMP_HIGH 1111 1111 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 183: Filter Output Clamp Low Register (Filteroclplo)
Sets the lower limit of filter output value. If calculated filter output falls below this _LOW 0000 threshold, the filter output will be set to OUTPUT_CLAMP_LOW 0000 0000 SNIU028A – February 2016 – Revised April 2016 Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 184: Filter Preset Register (Filterpreset)
4 = 18-bit Filter Data Register (after multiplication) 23-0 PRESET_VALUE 0000 Value to preset into selected register 0000 0000 0000 0000 0000 Filter SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 185: Loop Mux
CPCC Cycle Adjustment Light Load Analog PCM This chapter covers the Loop Mux registers. The modules have chapters of their own. SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 186 Constant Current / Constant Power ................5.12 Analog Peak Current Mode ................5.13 Automatic Cycle Adjustment ................5.14 Loop Mux Registers Reference Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 187: Front End Control Muxes (Fectrl0Mux, Fectrl1Mux, Fectrl2Mux)
DAC control function should be triggered just after the end of the EADC conversion to allow maximum DAC settling time. For DAC settling time, please refer to the UCD3138 device datasheet. The FECTRLxMUX registers also permit using the Nonlinear Select registers in the Filter to set the step points for Automatic Gain Shifting in the Front End.
Page 188: Filter Mux Register (Filtermux)
= 0; glben_store.bit.DPWM0_EN = 1; glben_store.bit.DPWM1_EN = 1; glben_store.bit.FE_CTRL0_EN = 1; LoopMuxRegs.GLBEN = glben_store; 2. Simply write to GLBEN: LoopMuxRegs.GLBEN = 0x13; Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 189: Pwm Global Period Register (Pwmglbprd)
There are added features which permit output of fixed size pulses in burst mode. This function is very application specific. Consult the reference firmware code provided with the UCD3138 EVM for the desired topology for further information.
Page 190: Ucd3138 Flux Balancing Approach
PCM_EN – enables peak current mode Refer to the reference firmware code provided with UCD3138PSFBEVM-027 and TI application note for Phase Shift Full Bridge peak current mode control implementation with UCD3138. 5.13 Automatic Cycle Adjustment The Loop Mux contains registers which control and monitor automatic cycle adjustment. It can be used to balance current between two legs of a parallel topology, such as a multiphase PFC.
Page 191: Front End Control 0 Mux Register (Fectrl0Mux)
0 = DPWM 2 Frame Sync not routed to Front End Control (Default) 1 = DPWM 2 Frame Sync routed to Front End Control SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 192 0 = DPWM 0 PWM-A trigger not routed to Front End Control (Default) 1 = DPWM 0 PWM-A trigger routed to Front End Control Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 193: Front End Control 1 Mux Register (Fectrl1Mux)
0 = DPWM 2 PWM-A trigger not routed to Front End Control (Default) 1 = DPWM 2 PWM-A trigger routed to Front End Control SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 194 0 = DPWM 0 PWM-A trigger not routed to Front End Control (Default) 1 = DPWM 0 PWM-A trigger routed to Front End Control Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 195: Front End Control 2 Mux Register (Fectrl2Mux)
0 = DPWM 2 PWM-A trigger not routed to Front End Control (Default) 1 = DPWM 2 PWM-A trigger routed to Front End Control SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 196 0 = DPWM 0 PWM-A trigger not routed to Front End Control (Default) 1 = DPWM 0 PWM-A trigger routed to Front End Control Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 197: Sample Trigger Control Register (Samptrigctrl)
0 = DPWM 0 Sample Trigger not routed to Front End Control 0 (Default) 1 = DPWM 0 Sample Trigger routed to Front End Control 0 SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 198: External Dac Control Register (Extdacctrl)
0 = External DAC Mode disabled. DAC 0 setpoint driven from Front End Control Module (Default) 1 = External DAC Mode enabled, DAC 0 setpoint driven by DAC0_SEL configuration Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 199: Filter Mux Register (Filtermux)
0 = DPWM 0 Switching Period (Default) 1 = DPWM 1 Switching Period 2 = DPWM 2 Switching Period 3 = DPWM 3 Switching Period SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 200 0 = Front End Module 0 provides data to Filter (Default) 1 = Front End Module 1 provides data to Filter 2 = Front End Module 2 provides data to Filter Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 201: Filter Kcomp A Register (Filterkcompa)
15-14 Reserved 13-0 KCOMP0 00 0000 14-bit value used in filter output calculations replacing the DPWM switching period 0111 value 1101 SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 202: Filter Kcomp B Register (Filterkcompb)
Reset Description 13-0 KCOMP2 00 0000 14-bit value used in filter output calculations replacing the DPWM switching period 0000 value 0000 Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 203: Dpwm Mux Register (Dpwmmux)
0 = DPWM 0 Sync (Default) 1 = DPWM 1 Sync 2 = DPWM 2 Sync 3 = DPWM 3 Sync SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 204 2 = Filter 2 Output Selected 3 = Constant Power Module Selected 4 = DPWM_ON_TIME value from Light Load Control Register Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 205: Constant Power Control Register (Cpctrl)
0 = Front End 0 Absolute Value Data Selected (Default) 1 = Front End 1 Absolute Value Data Selected 2 = Front End 2 Absolute Value Data Selected SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 206 CPCC_EN Constant Power Constant/Current Module Enable 0 = Constant Power/Constant Current Module disabled (Default) 1 = Constant Power/Constant Current Module enabled Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 207: Constant Power Nominal Threshold Register (Cpnom)
Configures INOM value used in Constant Power/Constant Current Calculations, LOWER 0000 when sensed value falls below NOM_CURRENT_LOWER in Constant Power mode, setpoint will switch to Constant Voltage mode SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 208: Constant Power Max Threshold Register (Cpmax)
Configures IMAX value used in Constant Power/Constant Current Calculations, when LOWER 0000 sensed value falls below MAX_CURRENT_LOWER in Max Current mode, setpoint will switch to Constant Power mode Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 209: Constant Power Configuration Register (Cpconfig)
NOM_VOLTAGE 00 0000 Configures V setpoint used in Constant Power/Constant Current Calculations in 0000 Constant Voltage mode (Loop Oring configuration selected) SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 210: Constant Power Max Power Register (Cpmaxpwr)
Description 19-0 MAX_POWER 0000 Configures P value used in Constant Power/Constant Current calculations in 0000 Constant Power mode 0000 0000 0000 Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 211: Constant Power Integrator Threshold Register (Cpintthresh)
24-bit signed value added to Current Loop Duty value to determine when to freeze 0000 Current Loop Integrator 0000 0000 0000 SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 212: Constant Power Firmware Divisor Register (Cpfwdivisor)
10-bit value used in Constant Power calculation when firmware value is selected in 0000 Bit 17 of Constant Power Control Register Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 213: Onstant Power Status Register (Cpstat)
0 = No transition from Constant Voltage to Constant Power detected 1 = Transition from Constant Voltage to Constant Power detected SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 214: Cycle Adjustment Control Register (Cycadjctrl)
2 = Front End Module 2 Error Data selected CYC_ADJ_EN Cycle Adjustment Calculation Enable 0 = Cycle Adjustment Calculation disabled (Default) 1 = Cycle Adjustment Calculation enabled Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 215: Cycle Adjustment Limit Register (Cycadjlim)
Calculation is clamped at the lower limit, if calculated result falls below the lower 0000 limit. LSB resolution equals High Frequency Oscillator period/16. SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 216: Cycle Adjustment Status Register (Cycadjstat)
2 error samples 15-10 Reserved 00 0000 CYC_ADJ 10-bit signed value representing calculated error of the first 2 error samples received _ERROR Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 217: Global Enable Register (Glben)
DPWM0_EN Global Firmware Enable for DPWM 0 Module 0 = DPWM 0 Module Disabled (Default) 1 = DPWM 0 Module Enabled SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 218: Pwm Global Period Register (Pwmglbprd)
Global PWM Period value, overriding DPWM Period settings when global PWM 0000 period is selected within each DPWM module 0000 Reserved 0000 Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 219: Sync Control Register (Syncctrl)
Configure direction of Sync pin 0 = Sync pin configured as an output pin 1 = Sync pin configured as an input pin (Default) SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 220: Light Load Control Register (Llctrl)
1 = Filter 1 data selected 2 = Filter 2 data selected LL_EN EADC-based Light Load Mode Enable 0 = Light Load Mode disabled (Default) 1 = Light Load Mode enabled Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 221: Light Load Enable Threshold Register (Llenthresh)
00 0000 Filter data threshold where constant width DPWM pulses are enabled when filter _THRESH 0000 000 data exceeds threshold 0000 SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 222: Light Load Disable Threshold Register (Lldisthresh)
00 0000 Filter data threshold where constant width DPWM pulses are disabled when filter _THRESH 0000 data falls below threshold 0000 0000 Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 223: Peak Current Mode Control Register (Pcmctrl)
1 = Filter 1 data selected 2 = Filter 2 data selected 3 = Constant Power/Constant Current data selected Reserved 0000 SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 224: Analog Peak Current Mode Control Register (Apcmctrl)
Analog Peak Current Mode Control Module Enable 0 = Analog Peak Current Mode Control Module disabled (Default) 1 = Analog Peak Current Mode Control Module enabled Loop Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 225: Loop Mux Test Register (Loopmuxtest) (Test Use Only)
0 = 1x Gain, 8mV/LSB 1 = 2x Gain, 4mV/LSB 2 = 4x Gain, 2mV/LSB 3 = 8x Gain, 1mV/LSB (Default) SNIU028A – February 2016 – Revised April 2016 Loop Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 226: Ucd3138 Fault Handling System
Even though most of the control for fault response action is based in the DPWM registers, it is discussed in this section (in this way all information relating to the Fault information is available in one location). Here is an overview of the fault handling system in the UCD3138: Fault Fault Detection...
Page 227 ................... DPWM Fault Action ................IDE / DCM Detection Control ................6.10 Oscillator Failure Detection ................6.11 Fault Mux Registers Reference SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 228: Ucd3138 Analog Comparator Control
The ACOMP_x_OUT_EN bit when set, puts the DAC value out on the ADC pin, which can be used as an external reference. Consult the UCD3138 device datasheet for additional information. When this bit is enabled, obviously the comparator output signals are not valid.
Page 229: Analog Comparator Ramp
There is also a DCOMPCNTSTAT register which gives the value in each of the counters. This register is read only. SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 230: Fault Pin Configuration
FaultMuxRegs.DPWM0FAULTDET.bit.PWMA_ACOMP_B_EN = 1; //Connect analog comparator B to DPWM0 fault A FaultMuxRegs.DPWM0FAULTDET.bit.PWMB_ACOMP_B_EN = 1; //Connect analog comparator B to DPWM0 fault B Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 231: Ucd3138 Dpwm Fault Action
(B_MAX_COUNT) Fault Enable (ALL_FAULT_EN) Edge Generation Figure 6-3. UCD3138 DPWM Fault Action This drawing fits in with the overview of the DPWM in Figure 2-1. The portion expanded here is the fault handler portion. The connection of the CLIM/CBC signal to the Timing Generation Module is also shown.
Page 232: Ide / Dcm Detection Control
Otherwise energy can flow back from the secondary to the primary. Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 233 The DCM_DETECT bit can be monitored in the FAULTMUXRAWSTAT register. The status of the interrupt can be read in the FAULTMUXINTSTAT register. The interrupt is enabled by DCM_INT_EN in the IDECTRL register. SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 234: 6.10 Oscillator Failure Detection
LFO fault detection status and interrupt status. 6.11 Fault Mux Registers Reference 6.11.1 Analog Comparator Control 0 Register (ACOMPCTRL0) Address 00030000 Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 235: Analog Comparator Control 0 Register (Acompctrl0)
Analog Comparator A Polarity 0 = Comparator result enabled when input falls below threshold 1 = Comparator result enabled when input exceeds threshold (Default) SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 236 1 = Enables Analog Comparator A Interrupt generation ACOMP_EN Analog Comparators Enable 0 = Analog Comparators Disabled (Default) 1 = Analog Comparators Enabled Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 237: Analog Comparator Control 1 Register (Acompctrl1)
0 = Comparator Reference of 19.53125 mV (Default) 1 = Comparator Reference of 39.0625 mV …….. 127 = Comparator Reference of 2.5 V Reserved SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 238 Analog Comparator C Interrupt Enable 0 = Disables Analog Comparator C Interrupt generation (Default) 1 = Enables Analog Comparator C Interrupt generation Reserved Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 239: Analog Comparator Control 2 Register (Acompctrl2)
0 = Comparator Reference of 19.53125 mV (Default) 1 = Comparator Reference of 39.0625 mV …….. 127 = Comparator Reference of 2.5 V Reserved SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 240 0 = Disables output of Comparator DAC E onto AD pin (Default) 1 = Enables output of Comparator DAC E onto AD pin Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 241: Analog Comparator Control 3 Register (Acompctrl3)
0 = Disables output of Comparator DAC G onto AD pin (Default) 1 = Enables output of Comparator DAC G onto AD pin SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 242: External Fault Control Register (Extfaultctrl)
1 = Fault Detection Enabled FAULT0_DET_EN FAULT[0] Pin Detection Enable 0 = Fault Detection Disabled (Default) 1 = Fault Detection Enabled Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 243: Fault Mux Interrupt Status Register (Faultmuxintstat)
Analog Comparator F Interrupt Status, cleared by read of status register 0 = Comparator threshold interrupt inactive 1 = Comparator threshold interrupt active SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 244 Analog Comparator A Interrupt Status, cleared by read of status register 0 = Comparator threshold interrupt inactive 1 = Comparator threshold interrupt active Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 245: Fault Mux Raw Status Register (Faultmuxrawstat)
1 = Comparator threshold exceeded ACOMP_F Analog Comparator F Raw Result 0 = Comparator threshold not exceeded 1 = Comparator threshold exceeded SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 246 1 = Comparator threshold exceeded ACOMP_A Analog Comparator A Raw Result 0 = Comparator threshold not exceeded 1 = Comparator threshold exceeded Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 247: Comparator Ramp Control 0 Register (Compramp0)
0 = DPWM 1 trigger not routed to Analog Comparator Ramp 0 (Default) 1 = DPWM 1 trigger routed to Analog Comparator Ramp 0 SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 248 1 = DPWM 0 trigger routed to Analog Comparator Ramp 0 RAMP_EN Enable for Analog Comparator Ramp 0 0 = Analog Comparator Ramp disabled (Default) 1 = Analog Comparator Ramp enabled Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 249: Digital Comparator Control 0 Register (Dcompctrl0)
1 = Enables Digital Comparator 0 10-0 THRESH 000 0000 Sets the digital comparator threshold, 11-bit signed value with resolution of 0000 1.5625mV/bit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 250: Digital Comparator Control 1 Register (Dcompctrl1)
1 = Enables Digital Comparator 0 10-0 THRESH 000 0000 Sets the digital comparator threshold, 11-bit signed value with resolution of 0000 1.5625mV/bit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 251: Digital Comparator Control 2 Register (Dcompctrl2)
1 = Enables Digital Comparator 0 10-0 THRESH 000 0000 Sets the digital comparator threshold, 11-bit signed value with resolution of 0000 1.5625mV/bit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 252: Digital Comparator Control 3 Register (Dcompctrl3)
1 = Enables Digital Comparator 3 10-0 THRESH 000 0000 Sets the digital comparator threshold, 11-bit signed value with resolution of 0000 1.5625mV/bit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 253: Digital Comparator Counter Status Register (Dcompcntstat)
Current value of Digital Comparator 2 detection counter 15-8 DCOMP1_CNT Current value of Digital Comparator 1 detection counter DCOMP0_CNT Current value of Digital Comparator 0 detection counter SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 254: Dpwm 0 Current Limit Control Register (Dpwm0Clim)
Enables Analog Comparator E result for DPWM 0 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 255 Enables Analog Comparator A result for DPWM 0 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 256: Dpwm 0 Fault Ab Detection Register (Dpwm0Fltabdet)
Table 6-15. DPWM 0 Fault AB Detection Register (DPWM0FLTABDET) Register Field Descriptions Field Type Reset Description DCOMP3_EN DCOMP2_EN DCOMP1_EN DCOMP0_EN FAULT3_EN FAULT2_EN FAULT1_EN FAULT0_EN ACOMP_G_EN ACOMP_F_EN ACOMP_E_EN ACOMP_D_EN ACOMP_C_EN ACOMP_B_EN ACOMP_A_EN Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 257: Dpwm 0 Fault Detection Register (Dpwm0Faultdet)
Enables Analog Comparator G result for DPWM 0 PWM-B Fault detection _G_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 258 Enables Analog Comparator G result for DPWM 0 PWM-A Fault detection _G_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 259 Enables Analog Comparator A result for DPWM 0 PWM-A Fault detection _A_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 260: Dpwm 1 Current Limit Control Register (Dpwm1Clim)
Enables Analog Comparator E result for DPWM 2 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 261 Enables Analog Comparator A result for DPWM 2 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 262: Dpwm 1 Fault Ab Detection Register (Dpwm1Fltabdet)
Enables Analog Comparator D result for DPWM 2 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 263 Enables Analog Comparator A result for DPWM 2 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 264: Dpwm 1 Fault Detection Register (Dpwm1Faultdet)
Enables Analog Comparator G result for DPWM 0 PWM-B Fault detection _G_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 265 Enables Analog Comparator G result for DPWM 0 PWM-A Fault detection _G_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 266 Enables Analog Comparator A result for DPWM 0 PWM-A Fault detection _A_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 267: Dpwm 2 Current Limit Control Register (Dpwm2Clim)
Enables Analog Comparator E result for DPWM 2 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 268 Enables Analog Comparator A result for DPWM 2 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 269: Dpwm 2 Fault Ab Detection Register (Dpwm2Fltabdet)
0 = Analog Comparator result disabled for Fault AB detection (Default) 1 = Analog Comparator result enabled for Fault AB detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 270 0 = Analog Comparator result disabled for Fault AB detection (Default) 1 = Analog Comparator result enabled for Fault AB detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 271: Dpwm 2 Fault Detection Register (Dpwm2Faultdet)
Enables Analog Comparator G result for DPWM 2 PWM-B Fault detection _G_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 272 Enables Analog Comparator F result for DPWM 2 PWM-A Fault detection _F_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 273 Enables Analog Comparator A result for DPWM 2 PWM-A Fault detection _A_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 274: Dpwm 3 Current Limit Control Register (Dpwm3Clim)
Enables Analog Comparator E result for DPWM 3 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 275 Enables Analog Comparator A result for DPWM 3 Current Limit 0 = Analog Comparator result disabled for current limit (Default) 1 = Analog Comparator result enabled for current limit SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 276: Dpwm 3 Fault Ab Detection Register (Dpwm3Fltabdet)
0 = Analog Comparator result disabled for Fault AB detection (Default) 1 = Analog Comparator result enabled for Fault AB detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 277 0 = Analog Comparator result disabled for Fault AB detection (Default) 1 = Analog Comparator result enabled for Fault AB detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 278: Dpwm 3 Fault Detection Register (Dpwm3Faultdet)
Enables Analog Comparator G result for DPWM 3 PWM-B Fault detection _G_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 279 Enables Analog Comparator F result for DPWM 3 PWM-A Fault detection _F_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 280 Enables Analog Comparator A result for DPWM 3 PWM-A Fault detection _A_EN 0 = Analog Comparator result disabled for fault detection (Default) 1 = Analog Comparator result enabled for fault detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 281: Hfo Fail Detect Register (Hfofaildet)
0 = Disables High Frequency Oscillator Failure Detection (Default) 1 = Enables High Frequency Oscillator Failure Detection SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 282: Lfo Fail Detect Register (Lfofaildet)
0 = Disables Low Frequency Oscillator Failure Detection (Default) 1 = Enables Low Frequency Oscillator Failure Detection Fault Mux SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 283: Ide Control Register (Idectrl)
IDE Mode. IDE_KD is configured in 4.9 format, with the integer portion of the KD 0000 value ranging from 0 to 15 and 9 fractional bits available for the pulse width calculation. SNIU028A – February 2016 – Revised April 2016 Fault Mux Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 284: Gio Module
External Interrupt Enable Register (EXTINTENA) ..........7.11 External Interrupt Polarity Register (EXTTINTPOL) ..........7.12 External Interrupt Pending Register (EXTINTPEND) ...................... 7.13 References GIO Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 285: Fault Io Direction Register (Faultdir)
FAULT[0] Pin Configuration 0 = FAULT[0] pin configured as an input pin (Default) 1 = FAULT[0] pin configured as an output pin SNIU028A – February 2016 – Revised April 2016 GIO Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 286: Fault Input Register (Faultin)
1 = FAULT[1] pin driven high FLT0_IN Input Value of FAULT[0] Pin 0 = FAULT[0] pin driven low 1 = FAULT[0] pin driven high GIO Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 287: Fault Output Register (Faultout)
0 = FAULT[0] pin driven low when configured as output (Default) 1 = FAULT[0] pin driven high when configured as output SNIU028A – February 2016 – Revised April 2016 GIO Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 288: Fault Interrupt Enable Register (Faultintena)
1 = Interrupt enabled for FAULT[1] pin FLT0_INT_EN FAULT[0] Interrupt Enable 0 = Interrupt disabled for FAULT[0] pin (Default) 1 = Interrupt enabled for FAULT[0] pin GIO Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 289: Fault Interrupt Polarity Register (Faultintpol)
FLT0_INT_POL FLT0_INT_POL– FAULT[0] Interrupt Polarity Select 0 = Interrupt generated on falling edge (Default) 1 = Interrupt generated on rising edge SNIU028A – February 2016 – Revised April 2016 GIO Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 290: Fault Interrupt Pending Register (Faultintpend)
FAULT[0] has caused an interrupt. Writing a 1 to a bit will clear the interrupt flag 0 = No Interrupt detected (Default) 1 = Interrupt pending GIO Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 291: External Interrupt Direction Register (Extintdir)
EXT-INT Pin Configuration 0 = EXT-INT pin configured as an input pin (Default) 1 = EXT-INT pin configured as an output pin SNIU028A – February 2016 – Revised April 2016 GIO Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 292: External Interrupt Input Register (Extintin)
Input Value of EXT-INT Pin 0 = EXT-INT pin driven low in GPIO mode 1 = EXT-INT pin driven high in GPIO mode GIO Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 293: External Interrupt Output Register (Extintout)
Type Reset Description EXT_INT_OUT EXT-INT Pin Output Value 0 = EXT-INT pin driven low (Default) 1 = EXT-INT pin driven high SNIU028A – February 2016 – Revised April 2016 GIO Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 294: External Interrupt Enable Register (Extintena)
Reset Description EXT_INT_EN EXT-INT Interrupt Enable 0 = Interrupt disabled for EXT-INT pin (Default) 1 = Interrupt enabled for EXT-INT pin GIO Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 295: External Interrupt Polarity Register (Exttintpol)
Description EXT_INT_POL EXT-INT Interrupt Polarity Select 0 = Interrupt generated on falling edge (Default) 1 = Interrupt generated on rising edge SNIU028A – February 2016 – Revised April 2016 GIO Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 296: External Interrupt Pending Register (Extintpend)
EXT-INT has caused an interrupt. Writing a 1 to a bit will clear the interrupt flag. 0 = No Interrupt detected (Default) 1 = Interrupt pending 7.13 References 1. UCD3138 ARM and Digital System Programmer’s Manual (SLUU996) 2. UCD3138 ARM and Digital System Programmer’s Manual (SLUU994) 3. UCD3138 Device Datasheet (SLUSAP2) GIO Module SNIU028A –...
Page 297: Adc12 Control Block Diagram
Chapter 8 SNIU028A – February 2016 – Revised April 2016 ADC12 Overview The ADC 12 in UCD3138 digital controller is a 12 bit, high speed analog to digital converter. It comes equipped with the following features: • Typical conversion speed of 267 ksps •...
Page 298 Usage of Sample and Hold Circuitry for High Impedance Measurement ................8.16 ADC Configuration Examples ............. 8.17 Useful C Language Statement Examples ....................8.18 ADC Registers ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 299: Adc12 Input Impedance Model
ADC12 Input Impedance Model Figure 8-2 shows a simplified model of the input circuit of UCD3138 ADC12. Figure 8-2. ADC12 Input Impedance Model The first portion is a 16-to-1 multiplexer that selects the channel to be converted. The second portion is the sample and hold circuit that is controlled by the control block of ADC12.
Page 300: Impedance Test Setup
UCD3138 ADC12 can, the input impedance is around 300kohm; at a sampling frequency of below 150kHz, the channel impedance is above 3Mohm. This data can be used as a general guideline of designing proper input R for the UCD3138 ADC12, or determine a proper operation frequency for a given R.
Page 301: S/H Capacitor Charge Vs. Settling Time
But when source impedance is high, channel to channel crosstalk can be observed easily. High source impedance Low source impedance Figure 8-8. Channel to Channel Crosstalk SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 302: Adc Control Register (Adcctrl)
S/H capacitor to discharge. Thus the voltage remaining on the S/H capacitor will affect the next conversion. Generally, for UCD3138, several ADC channels are used for different monitoring purposes. When designing the ADC input circuit, it is highly recommended to avoid high impedance node, because high impedance node may result in extra impedance roll-offs due to crosstalk.
Page 303: Sequencing
ADC12 block are referred to by channel numbers. 14 of the ADC Channels are connected to external pins. The remaining 2 channels are tied to an internal temperature sensor and an internal test channel. The following table details the channel mapping utilized on UCD3138. Channel Number...
Page 304: Ucs3138 Digital Comparators Control Block Diagram
For example, both statements below will clear all of the latched results. int scrap; scrap = AdcRegs.ADCCOMPRESULT.all; scrap = AdcRegs.ADCCOMPRESULT.bit.DCOMP3_LO_INT; ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 305: 8.10 Adc Averaging
In order to activate the internal temperature sensor the following bit in TEMPSENCTRL register at Chapter 8 need to be cleared. MiscAnalogRegs.TEMPSENCTRL.bit.TEMP_SENSE_DIS = 0; SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 306: Temp Sensor Control Register (Tempsenctrl)
Therefore it is recommended to use a read- modify-write technique to clear or set this bit. ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 307: Pmbus Control Register 3 (Pmbctrl3)
PMBus Addressing www.ti.com 8.13 PMBus Addressing UCD3138 offers two constant current sources for excitation of resistors used for setting the PMBus address, as shown in Figure 8-13. The two current sources are connected to CH-0 and CH-1 of ADC-12 and are disabled as default. The nominal current is preset to 10 µA.
Page 308: Pmbus Addressing
Table 8-3. Selection of “Dual Sample and Hold” Channel BYPASS_EN[2:0] value Selected Dual BYPASS_EN[2] BYPASS_EN[1] BYPASS_EN[0] in hex Sample/Hold Channel Channel 0 Channel 1 Channel 2 ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 309: Adc Control Register (Adcctrl)
There is only one conversion unit in UCD3138 ADC. But there are two S/H units to enable dual sample and hold function. The first one is the normal one we used for all channels. The second one shown in Figure 8-15 the dual sample and hold S/H.
Page 310: Dual Sample And Hold Circuitry In Adc12
//put AD04 on sequence 0 SEQ0_SH = 1; //enable AD04 to do dual sample and hold with AD01 SEQ1 = 1; //put AD01 on sequence1 ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 311: Adc Configuration Examples
0 to 1. The conversion results are placed in the ADC result buffers. SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 312: Single Sweep Operation
The function also starts a new sequence of measurements that can be read when the function is called next time. ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 313: Auto-Triggered Conversions
Requirement: Auto convert 6 currents (I ,…I ) every 100us synchronized to the external trigger. Figure 8-17. SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 314: Start/Stop Operation (External Trigger)
Field Name Channel Select Value SEQ00 SEQCHSEL0 SEQ01 14:10 SEQ02 Bits Field Name Channel Select Value SEQ03 SEQCHSEL1 SEQ04 14:10 SEQ05 ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 315: 8.17 Useful C Language Statement Examples
//Means: The fifth comparator is configured to compare the average data from ADC12 and not the raw data AdcRegs.ADCCOMPEN.bit.COMP3_UP_INT_EN = 1; SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 316: Adc Control Register (Adcctrl)
External Trigger Enable, conversions are started using the external trigger as selectable by the EXT_TRIG_SEL bits. 0 = Disable External Trigger capability (Default) 1 = Enable External Trigger capability ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 317: Adc Control Register (Adcctrl) Register Field Descriptions
0 = Disable End-of-Conversion Interrupt (Default) 1 = Enable End-of-Conversion Interrupt ADC_EN ADC12 Enable Control 0 = Disables ADC (Default) 1 = Enables ADC SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 318: Adc Status Register (Adcstat)
1 = End-of-conversion interrupt found ADC_INT End-of-conversion interrupt flag, latched version 0 = No End-of-conversion interrupt detected 1 = End-of-conversion interrupt found ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 319: Adc Test Control Register (Adctstctrl)
ADC Test Mode Enable 0 = Disables ADC Test Mode (Default) 1 = Enables ADC Test Mode for enabling controls in this register SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 320: Adc Sequence Select Register 0 (Adcseqsel0)
Channel to be converted first 0000 = Channel 0 selected (Default) 0001 = Channel 1 selected ……. 1111 = Channel 15 selected ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 321: Adc Sequence Select Register 1 (Adcseqsel1)
Channel to be converted fifth 0000 = Channel 0 selected (Default) 0001 = Channel 1 selected ……. 1111 = Channel 15 selected SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 322: Adc Sequence Select Register 2 (Adcseqsel2)
Channel to be converted ninth 0000 = Channel 0 selected (Default) 0001 = Channel 1 selected ……. 1111 = Channel 15 selected ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 323: Adc Sequence Select Register 3 (Adcseqsel3)
Channel to be converted thirteenth 0000 = Channel 0 selected (Default) 0001 = Channel 1 selected ……. 1111 = Channel 15 selected SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 324: Adc Result Registers 0-15 (Adcresultx, X=0:15)
Table 8-12. ADC Result Registers 0-15 (ADCRESULTx, x=0:15) Register Field Descriptions Field Type Reset Description 11-0 RESULT Each sequence has a dedicated result register. ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 325: Adc Averaged Result Registers 0-5 (Adcavgresultx, X=0:15)
Table 8-13. ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15) Register Field Descriptions Field Type Reset Description 11-0 RESULT First 6 ADC Results have an averaged result SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 326: Adc Digital Compare Limits Register 0-5 (Adccomplimx, X=0:5)
Digital Compare Interrupt Flag is set (bit 22 of ADC Control Register 1). 0000 Results of comparison can be read from the ADC Digital Compare Results Register (see Section 4.12). ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 327: Adc Digital Compare Enable Register (Adccompen)
0 = Interrupt generation disabled on result below lower limit (Default) 1 = Interrupt generation enabled on result below lower limit SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 328 0 = Comparator Disabled (Default) 1 = Comparator Enabled COMP0_EN Digital Comparator 0 Enable 0 = Comparator Disabled (Default) 1 = Comparator Enabled ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 329: Adc Digital Compare Results Register (Adccompresult)
1 = Limit exceeded DCOMP1_UP_RAW Digital Comparator 1 Upper Limit Raw Result 0 = Limit not exceeded 1 = Limit exceeded SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 330 1 = Limit exceeded DCOMP0_LO_INT Digital Comparator 0 Lower Limit Interrupt Result, cleared on read 0 = Limit not exceeded 1 = Limit exceeded ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 331: Adc Averaging Control Register (Adcavgctrl)
3 = Moving average of 32 samples AVG2_EN ADC Averaging Module 4 Enable 0 = ADC Averaging Disabled (Default) 1 = ADC Averaging Enabled SNIU028A – February 2016 – Revised April 2016 ADC12 Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 332 3 = Moving average of 32 samples AVG0_EN ADC Averaging Module 0 Enable 0 = ADC Averaging Disabled (Default) 1 = ADC Averaging Enabled ADC12 Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 333: Advanced Power Management Control Functions
Interaction with a Single Pin ................9.11 Interaction with Multiple Pins ......................9.12 Registers ................9.13 Trim and Test Registers - Note SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 334: Package Id Information
• PWM bus current sharing • Master/Slave current sharing A simplified schematic of the current sharing circuitry integrated in UCD3138 is shown in the drawing below: Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback...
Page 335: Tolerance
The period and the duty of 8-bit PWM current source and the state of the θ1 and θ2 switches can be controlled through the current sharing control register (CSCTRL). For more details please refer to Application Note on UCD3138 Current Sharing. SNIU028A – February 2016 – Revised April 2016...
Page 336: Package Id Register (Pkgid)
Please refer to Section 9.8.7 and Section 3.7 of UCD3138 device datasheet for more information. Miscellaneous Analog Control Registers 9.8.1 Package ID Register (PKGID) Address FFF7F010 Figure 9-4.
Page 337: Brownout Register (Brownout)
1 = Brownout Interrupt enabled COMP_EN Brownout Comparator Enable 0 = Brownout comparator logic disabled (Default) 1 = Brownout comparator logic enabled SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 338: Temp Sensor Control Register (Tempsenctrl)
Therefore you should use a read-modify-write technique to clear or set this bit. Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 339: Control
ALERT SCI_RX-1 SCI_RX-1 CONTROL Table 9-11. Bit 0: PMBUS_MUX_SEL – SCL/SDA Pins Mux Select I/O Pin SCI_TX-0 SCI_RX-0 SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 340: Current Sharing Control Register (Csctrl)
CSCTRL.bit.TEST_MODE Digital-PWM Tri-state or Slave mode PWM average current Bus ACTIVE Analog average current Bus or Master mode Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 341: Temperature Reference Register (Tempref)
Reference measurement taken during factory trim, ADC12 measurement of the 0000 internal temperature sensor at room temperature for use in offset calibration 0000 SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 342: Power Disable Control Register (Pwrdisctrl)
Clock Enable for DPWM 1 Module 0 = Disables clocks to DPWM 1 Module 1 = Enables clocks to DPWM 1 Module (Default) Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 343: Gpio Overview
GPIO Overview Majority of the pins in UCD3138 can be configured to serve as a general purpose input or output pin (GPIO). The only pins that can not be configured as GPIO pins are the Supply pins, Ground pins, ADC-12 analog input pins, EADC analog input pins and RESET pin.
Page 344: Interaction With A Single Pin
Example 2.2: configuration through Global I/O registers: MiscAnalogRegs.GLBIOEN.bit.FAULT2_IO_EN = 1; //Configure FAULT2 as GPIO MiscAnalogRegs.GLBIOOE.bit.FAULT2_IO_OE = 0; // 1 = output, 0 = input Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 345: Interaction With Multiple Pins
// check whether the ADC_EXT_TRIG pin or the SYNC pin are pulled high if( MiscAnalogRegs.GLBIOREAD.all & (ADC_EXT_TRIG_GLBIO_BIT_MASK | SYNC_GLBIO_BIT_MASK)) SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 346: Global I/O En Register (Gbioen)
SCI_TX[1] SYNC SCI_TX[0] DPWM3B SCI_RX[1] DPWM3A SCI_RX[0] DPWM2B TMR_CAP DPWM2A TMR_PWM[1] DPWM1B TMR_PWM[0] DPWM1A PMBUS-CLK DPWM0B PMBUS-DATA DPWM0A Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 347: Global I/O Oe Register (Glbiooe)
SCI_TX[1] SYNC SCI_TX[0] DPWM3B SCI_RX[1] DPWM3A SCI_RX[0] DPWM2B TMR_CAP DPWM2A TMR_PWM[1] DPWM1B TMR_PWM[0] DPWM1A PMBUS-CLK DPWM0B PMBUS-DATA DPWM0A SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 348: Global I/O Open Drain Control Register (Glbiood)
SCI_TX[1] SYNC SCI_TX[0] DPWM3B SCI_RX[1] DPWM3A SCI_RX[0] DPWM2B TMR_CAP DPWM2A TMR_PWM[1] DPWM1B TMR_PWM[0] DPWM1A PMBUS-CLK DPWM0B PMBUS-DATA DPWM0A Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 349: Global I/O Value Register (Glbioval)
SCI_TX[1] SYNC SCI_TX[0] DPWM3B SCI_RX[1] DPWM3A SCI_RX[0] DPWM2B TMR_CAP DPWM2A TMR_PWM[1] DPWM1B TMR_PWM[0] DPWM1A PMBUS-CLK DPWM0B PMBUS-DATA DPWM0A SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 350: Global I/O Read Register (Glbioread)
SCI_TX[1] SYNC SCI_TX[0] DPWM3B SCI_RX[1] DPWM3A SCI_RX[0] DPWM2B TMR_CAP DPWM2A TMR_PWM[1] DPWM1B TMR_PWM[0] DPWM1A PMBUS-CLK DPWM0B PMBUS-DATA DPWM0A Advanced Power Management Control Functions SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 351: Clock Trim Register (Clktrim) (For Factory Test Use Only, Except Hfo_Ln_Filter_En) Register
0 = High Frequency Oscillator Disabled 1 = High Frequency Oscillator Enabled (Default) SNIU028A – February 2016 – Revised April 2016 Advanced Power Management Control Functions Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 352: Pmbus Interface/I2C Interface
SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface The UCD3138 family has a powerful and flexible PMBus/I2C interface. It has support for master mode, but its primary use is in slave mode. Here are some of its features in slave mode: •...
Page 353: Pmbus Register Summary
– These settings are useful if the Master requires invalid data to be NACKed – They can be set dynamically as the message comes in. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 354: Initialization For I2C
The I2C bus is very similar to the PMBus. One difference is that the I2C has no maximum clock low time. The PMBus has a 35 msec maximum clock low time, and the UCD3138 PMBus interface automatically detect violations of this. If this functionality is not desired, you can set the CLK_LO_DIS bit in PMBCTRL3.
Page 355: Pmbus Slave Mode Command Examples
The start of the next message is included in the drawing. This shows the timing requirements if a second message follows with no delay. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 356 The timing between a write to the ACK register and the release of the clock stretch will be . The clock stretching is automatically provided by the hardware with no firmware action ACKWRITE required. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 357: Command With Pec
Figure 10-2. Command with PEC Address Wr A A Data Byte Command PEC_VALID DATA_RDY RD_BYTE_COUNT Figure 10-3. Write Command and Byte - No PEC SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 358: Write Command And Byte - With Pec
The PMBus hardware automatically provides clock stretching on the ACK for the 4th byte, if it is necessary. Here is the timing diagram: PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 359: Timing Diagram
2. DATA_RDY and RD_BYTE_COUNT cleared by read from PMBST, data read from RXBUF, 1 written to ACK bit. Clock stretch released. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 360: Slave Address Manual Ack For Write
Clock stretch will be cleared t after the ACK bit is written to. If the firmware is fast enough, no ACKWRITE clock stretch will occur. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 361: Manual Ack Command
This is especially true of the simplest case, which is I2C specific, not supported in the PMBus – read only. Here is the sequence diagram: SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 362: Simple Read With Full Automation
Up to 4 bytes can be read with the same number of firmware steps as 1 byte, taking advantage of the 4 byte TXBUF. Here is a sequence diagram for 4 bytes: PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 363: Simple Read Of 4 Bytes With Full Automation
DREQ1 fourth byte. 6. The firmware reads from PMBST, clearing the DATA_REQUEST bit. Since one byte is being sent out, SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 364: Slave Address Manual Ack On A Read Address
Address Rd SLAVE_ADDR_READY Write to ACK DATA_REQUEST Write to TXBUF Figure 10-13. Slave Address Manual ACK on a Read Address PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 365: Write/Read With Repeated Start
All byte sequences after the repeated start will be the same as described above in the simple read sequences after the start. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 366: Automatic Pec Addition
The UCD PMBus/I2C hardware assumes that the PEC will be the last byte in the message. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 367: Clock Stretch Timing For Read
For many applications, clock stretching is acceptable, but there may be requirements for minimal or no clock stretching. The UCD3138 family PMBus/I2C architecture permits this for some cases For example, write messages up to 3 bytes and command can be handled in one operation using the 4 byte buffer and automated ACK.
Page 368: Alert Response
Device Addr Figure 10-16. Alert Response The UCD3138 PMBus interface provides an automated handling of the ALERT Response. To enable it, set the ALERT_EN bit in PMBCTRL3. This will pull the ALERT pin low, and enable the ALERT response from the hardware. If MAN_SLAVE_ACK is not set, the hardware will automatically acknowledge the special ALERT address, and will automatically to the arbitration with the device address.
Page 369: Address Byte Timing
Slave Address (Stretch) PMBUS_CLK PMBUS_DATA UNIT_BUSY START SLAVE_ADDR_READY DATA_REQUEST(1) DREQ1 Write to ACK ACKWRITE DATA_REQUEST(2) DREQ2 Figure 10-18. Repeated Start Timing SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 370: Read Byte Timing
DRDY RD_BYTE_COUNT Figure 10-20. Write Byte Timing Data Byte PMBUS_CLK PMBUS_DATA PEC_VALID DATA_RDY RD_BYTE_COUNT Figure 10-21. Write Byte Stop Timing PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 371: Timing Parameters From Timing Diagrams
ACKed until the firmware has read the PMBHSA for the message. The next bit set in the status register will be either DATA_READY or DATA_REQUEST. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 372: Master Mode Operation Reference
Additional control bits within the Master Control Register enable various message protocols for PMBus applications. Protocols such as Process Call and Group Command Messages require additional programming with these bits. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 373: Quick Command Format
R/W bit and the optional PEC_EN into the Master Control Register. The R/W bit is enabled high to indicate a read message type (data transmitted from Slave to Master). SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 374: Write Byte W/O Pec Byte
PMBus. The firmware can wait for an End of Message interrupt from the interface to verify the accuracy of the message transmission. The Status Register indicates if the slave acknowledged the message properly. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 375: Read Byte W/O Pec Byte
PEC is enabled for the message, the PEC_VAL bit in the Status Register can be verified to check the accuracy of the received PEC byte from the Slave. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 376: Process Call W/O Pec Byte
Master is not recommended until the firmware requires a new message to be transmitted on the PMBus. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 377: Block Write W/O Pec Byte
Upon completion of the message, the PMBus Interface issues an EOM interrupt. The interface can be checked to verify the slave accepted the block of write data. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 378: Block Read W/O Pec Byte
The firmware may verify the received PEC upon detection of the End of Message interrupt. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 379: Block Write-Block Read Process Call W/O Pec Byte
Address, initiates the Alert Response message and provides the device address of the Slave requesting service. The device address will be found in the Receive Data Register following receipt of the EOM interrupt. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 380: Extended Command Write Byte W/O Pec Byte
Command Byte Ext Command Byte Device Addr Byte #0 Byte #1 Figure 10-51. Extended Command Read Word with PEC Byte PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 381: Group Command
On the UCD3138, and UCD3138064, this is the case. On the UCD3138A64 and UCD3138128 and all A versions, stopping the message in the middle of the byte should be handled correctly.
Page 382: Pmbus Control Register 1 (Pmbctrl1)
The firmware only needs to load the address, command words and data to be transmitted. PMBus Interface supports byte writes up to 255 bytes. PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 383 0 = Message is a write transaction (data from Master to Slave) (Default) 1 = Message is a read transaction (data from Slave to Master) SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 384: Pmbus Transmit Data Buffer (Pmbtxbuf)
Second data byte transmitted from Transmit Data Buffer 0000 BYTE0 0000 First data byte transmitted from Transmit Data Buffer 0000 PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 385: Pmbus Receive Data Register (Pmbrxbuf)
Third data byte received in Receive Data Buffer 15-8 BYTE1 Second data byte received in Receive Data Buffer BYTE0 First data byte received in Receive Data Buffer SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 386: Pmbus Acknowledge Register (Pmback)
Allows firmware to acknowledge or not acknowledge received data 0 = NACK received data (Default) 1 = Acknowledge received data, bit clears upon issue of ACK on PMBus PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 387: Pmbus Status Register (Pmbst)
RPT_START Repeated Start Flag 0 = No Repeated Start received by interface 1 = Repeated Start condition received by interface SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 388 3 = 3 bytes received. Data located in Receive Data Register, Bits 23-0 4 = 4 bytes received. Data located in Receive Data Register, Bits 31-0 PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 389: Pmbus Interrupt Mask Register (Pmbintm)
0 = Generates interrupt upon assertion of Bus Free flag 1 = Disables interrupt generation upon assertion of Bus Free flag (Default) SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 390: Pmbus Control Register 2 (Pmbctrl2)
3 = Three bytes valid, Bytes #0-2 (Bits 23:0 of Receive Data Register) 4 = Four bytes valid, Bytes #0-3 (Bits 31:0 of Receive Data Register) PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 391 Slave Address bits and the mask configured in the Slave Mask bits. If matching, the slave will acknowledge the device address. SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 392: Pmbus Hold Slave Address Register (Pmbhsa)
Stored device address acknowledged by the slave SLAVE_RW Stored R/W bit from address acknowledged by the slave 0 = Write Access 1 = Read Access PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 393: Pmbus Control Register 3 (Pmbctrl3)
Configures direction of PMBus clock pin in GPIO mode 0 = PMBus clock pin configured as output (Default) 1 = PMBus clock pin configured as input SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 394 0 = PMBus Alert is not driven by slave, pulled up high on PMBus (Default) 1 = PMBus Alert driven low by slave PMBus Interface/I2C Interface SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 395 PMBus Interface Synchronous Reset 0 = No reset of internal state machines (Default) 1 = Control state machines are reset to initial states SNIU028A – February 2016 – Revised April 2016 PMBus Interface/I2C Interface Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 396: Timer Module Overview
11.18 Watchdog Timer Example ............11.19 Warnings for Watchdog Status Register ................11.20 System Fault Recovery Basics ..............11.21 Timer Module Register Reference Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 397: T24 – 24 Bit Free-Running Timer With Capture And Compare
The internal clock is the default. To select the external clock source instead, execute this C equation: TimerRegs.T24CNTCTRL.bit.EXT_CLK_SEL = 1; All C code references in this document use standard TI header files, provided as part of the UCD3138 EVM (UCD3138PFCEVM-026, UCD3138LLCEVM-028 etc) reference firmware.
Page 398: T24 Capture Block
It can select from 4 signal sources: • TCAP – the default, dedicated pin • SCI_RX0 – useful for measuring the receive baud rate Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 399: T24 Compare Blocks
All of the interrupts from a specific timer are combined into one before being sent to the CIM interrupt module. Each timer has its own interrupt bit in the CIM. SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 400: T16Pwmx Prescaler And Counter
T16. Here is the C code to write to a compare data register: TimerRegs.T16PWM0CMP0DAT.bit.CMP_DAT = 100; Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 401: T16 Shadow Bit
It will also be necessary to write to all the interrupt flags which are set to clear the interrupt. SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 402: Using The T16 For A Timer Interrupt
TimerRegs.T16PWM0CNTCTRL.bit.SW_RESET = 1; //allow counter to run In UCD3138 the interrupt flags are not cleared automatically by hardware when the interrupt is serviced. Therefore the interrupt flag needs to be manually cleared by adding the following statement at the end of the relevant interrupt service routine.
Page 403: Watchdog Prescale And Counter
Other bits in the Watchdog Control register are not protected, however. For example, the WD_PERIOD bits can still be changed, as can the interrupt enable bits. Refer to Section 11.21 for details. SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 404: Watchdog Timer Example
This will generally have the effect of shutting down any power supply that is being controlled by the device. Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 405: 24-Bit Counter Data Register (T24Cntdat)
Table 11-1. 24-bit Counter Data Register (T24CNTDAT) Register Field Descriptions Field Type Reset Description 23-0 CNT_DAT Contains the 24-bit counter value SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 406: 24-Bit Counter Control Register (T24Cntctrl)
(set has priority versus clear). 0 = No counter overflow since last clear 1 = Counter overflow since last clear Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 407: 24-Bit Capture Channel Data Register (T24Capdat)
Table 11-3. 24-bit Capture Channel Data Register (T24CAPDAT) Register Field Descriptions Field Type Reset Description 23-0 CAP_DAT Contains the 24-bit input capture value SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 408: Bit Capture Channel Control Register (T24Capctrlx Or T24Capctrl
(set has priority versus clear). 0 = No valid capture event since last clear 1 = Valid capture event since last clear Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 409: 24-Bit Capture I/O Control And Data Register (T24Capio)
Controls data direction for TCAP or TCAP0 pin, when connected to chip I/O TCAP_0_DIR* 0 = TCAP pin configured as input (Default) 1 = TCAP pin configured as output SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 410: 24-Bit Output Compare Channel 0 Data Register (T24Cmpdat0)
Table 11-6. 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0) Register Field Descriptions Field Type Reset Description 23-0 CMP_DAT 0000 Contains the 24-bit output comparison value 0000 0000 0000 0000 0000 Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 411: 24-Bit Output Compare Channel 1 Data Register (T24Cmpdat1)
Table 11-7. 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1) Register Field Descriptions Field Type Reset Description 23-01 CMP_DAT 0000 Contains the 24-bit output comparison value 0000 0000 0000 0000 0000 SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 412: 24-Bit Output Compare Channel 0 Control Register (T24Cmpctrl0)
(set has priority versus clear). 0 = No compare event since last clear 1 = Compare event since last clear Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 413: 24-Bit Output Compare Channel 1 Control Register (T24Cmpctrl1)
(set has priority versus clear). 0 = No compare event since last clear 1 = Compare event since last clear SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 414: Pwmx Counter Data Register (T16Pwmxcntdat)
Table 11-10. PWMx Counter Data Register (T16PWMxCNTDAT) Register Field Descriptions Field Type Reset Description 15-0 CNT_DAT Contains the 16-bit counter value. Read-only. Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 415: Pwmx Counter Control Register (T16Pwmxcntctrl)
0 = No PWM counter overflow since last clear 1 = PWM counter overflow since last clear SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 416: Pwmx 16-Bit Compare Channel 0-1 Data Register (T16Pwmxcmpydat)
T16PWMxCMP0DAT and T16PWMxCMP1DAT contain the same value, the interrupt and pin behavior is controlled by output compare channel 0 (T16PWMxCMP0DAT has priority over T16PWMxCMP1DAT). Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 417: Pwmx Compare Control Register (T16Pwmxcmpctrl)
Note – Bits indicated with a * are only available for 16 bit timers which have an external pin associated with them. On the UCD3138 and most family members, this is only PWM0 and PWM1. On the UCD3138128 and UCD3138A64 80 pin devices, all 4 timers have an external pin.
Page 418 (set has priority versus write clear). 0 = No compare event since last clear 1 = Compare event since last clear Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 419: Watchdog Status (Wdst)
Watchdog Event Interrupt Status, cleared on read of Watchdog Status Register 0 = Watchdog Timer has not reached terminal count 1 = Watchdog Timer has reached terminal count SNIU028A – February 2016 – Revised April 2016 Timer Module Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 420: Watchdog Control (Wdctrl)
This bit resets the watchdog counters. This bit self clears and if the enables are set, the counters restart counting. 0 = Watchdog counters enabled (Default) 1 = Watchdog counters reset Timer Module Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 421: Uart Overview
SNIU028A – February 2016 – Revised April 2016 UART Overview UCD3138 has two UART modules capable of independently communicating toward two separate peers. Having more than one UART module is also especially useful for power supplies than need to communicate with an isolated section (eg. with the digital PFC controller, or a Power Metering ASIC in offline AC/DC power supplies) through opto-isolators.
Page 422: Uart Frame Format
12.2 Asynchronous Timing Mode Asynchronous timing mode is the only mode supported in UCD3138. In the asynchronous timing mode, each bit in a frame has a duration of 8 UART baud clock periods. Each bit therefore consists of 8 samples (one for each clock period).
Page 423: Uart Interrupts
However, the exact source of an error interrupt can be determined by checking the parity error (PE), frame error (FE), overrun error (OE), break-detect (BRKDT), and wake-up (WAKEUP) flags also located in UARTRXST. SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 424: Transmit Interrupt
When not enabled, the interrupts are not asserted; however, polled operation of the UART is still possible because the interrupt flags continue to indicate module events. The UART module generates three interrupt requests to the UCD3138 system module: one each for transmitter, receiver, and error interrupts. Each of these interrupts must also be configured in the UCD3138 system module before operation.
Page 425 If WAKEUP_INT_ENA (UARTCTRL3.2) is set, an error interrupt is generated when bus activity on the RX line either prevents power-down mode from being entered or RX line activity causes an exit from power- down mode. SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 426: Uart Control Register 0 (Uartctrl0)
1 = One parity bit included in each frame SYNC_MODE Selects between Synchronous mode and Asynchronous mode 0 = Synchronous (Not supported in UCD3138, set this bit always to one) 1 = Asynchronous ADDR_MODE Selects between Idle and Address Bit Mode...
Page 427: Uart Receive Status Register (Uartrxst)
1 = UART Receiver has entered wakeup state RX_ENA Turns on UART Receiver 0 = UART Receiver disabled (Default) 1 = UART Receiver enabled SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 428: Uart Transmit Status Register (Uarttxst)
1 = UART Transmitter Wakeup enabled TX_ENA Turns on TX module 0 = UART Transmitter Disabled (Default) 1 = UART Transmitter Enabled UART Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 429: Uart Control Register 3 (Uartctrl3)
ERR_INT_ENA Enables UART Receiver Error Interrupt 0 = Disables UART Receiver Error Interrupt (Default) 1 = Enables UART Receiver Error Interrupt SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 430: Uart Interrupt Status Register (Uartintst)
0 = No UART Receiver Errors detected 1 = Frame Error or Overrun error or Parity Error or Broken Circuit error received from UART Receiver UART Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 431: Uart Baud Divisor High Byte Register (Uarthbaud)
Table 12-7. UART Baud Divisor High Byte Register (UARTHBAUD) Register Field Descriptions Field Type Reset Description BAUD_DIV_H 0000 Sets the high byte of the 24 bit baud rate selector 0000 SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 432: Uart Baud Divisor Middle Byte Register (Uartmbaud)
Table 12-8. UART Baud Divisor Middle Byte Register (UARTMBAUD) Register Field Descriptions Field Type Reset Description BAUD_DIV_M 0000 Sets the middle byte of the 24 bit baud rate selector 0000 UART Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 433: Uart Baud Divisor Low Byte Register (Uartlbaud)
Table 12-9. UART Baud Divisor Low Byte Register (UARTLBAUD) Register Field Descriptions Field Type Reset Description BAUD_DIV_L 0000 Sets the low byte of the 24 bit baud rate selector 0000 SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 434: Uart Receive Buffer (Uartrxbuf)
Table 12-10. UART Receive Buffer (UARTRXBUF) Register Field Descriptions Field Type Reset Description RXDAT Contains the last data byte received from the UART Receiver UART Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 435: Uart Transmit Buffer (Uarttxbuf)
Table 12-11. UART Transmit Buffer (UARTTXBUF) Register Field Descriptions Field Type Reset Description TXDAT 0000 Contains the data byte to be transmitted by the UART Transmitter 0000 SNIU028A – February 2016 – Revised April 2016 UART Overview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 436: Uart I/O Control Register (Uartioctrlsclk, Uartioctrlrx, Uartioctrltx)
1 = Baud Clock for SCLK, Normal operation for SCI_RX/SCI_TX IO_DIR Pin direction when configured as GPIO 0 = Input (Default) 1 = Output UART Overview SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 437: Boot Rom And Boot Flash
Boot ROM and Boot Flash The Boot ROM and the Boot Flash are key elements in the use of the UCD3138, which provide capability to examine, and modify memory and registers and download programs into the device. They also offer security for production programs.
Page 438: Boot Rom Function
If the checksum is not valid, the Boot ROM will permit examination and modification of memory and peripherals. 13.1.1 Initializing UCD3138 The Boot ROM performs several initializations on the UCD3138. The most important one is memory map initialization. This is described in Chapter 5 Chapter 13.1.2 Verifying Checksums...
Page 439: Ucd3138 Boot Rom Execution After Power-On/Reset
Boot ROM Function www.ti.com Figure 13-1. UCD3138 Boot ROM Execution After Power-On/Reset The Boot Flash Checksum at address 0x07FC provides more sophisticated field upgradeability. It is useful for cases which require an upgrade: • Via PMBus, but at a different PMBus address from the ROM’s standard PMBus address •...
Page 440: Boot Flash
2. Don’t program the checksum until the backdoor has been tested with this version of the program. More detailed information is available in Chapter Boot ROM and Boot Flash SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 441: Using Boot Rom Pmbus Interface
13.2 Memory Read Functionality A total of 4 PMBus command bytes have been assigned for read functionality in the UCD3138 Boot ROM. 3 of these messages utilize a read format, in which the PMBus Master provides an address and command byte to the UCD3138 and expects read data returned by the slave.
Page 442: Read 4 Bytes
Read Version message by sending a device address and a command byte of 0xEC. The Boot ROM will interpret the command byte and return the block size of 4 bytes, the current version number and the PEC byte for the message. The current version for the version of UCD3138 should be 0x00030002. Start Device Address &...
Page 443: Rom Version For The Other Members Of The Ucd3138 Family
0x00050001 13.4 Memory Write Functionality A total of 6 PMBus command bytes have been assigned for write functionality in the UCD3138 Boot ROM. Each of these write-based PMBus messages utilizes a write format, in which the PMBus Master provides an address, the command byte and data bytes to the PMBus Slave (UCD3138).
Page 444: Write Next 16 Bytes
In this case, 200 µsec should be allowed before starting the next message. 13.5 Flash Functions In addition to the ability to read and write internal memory map locations, the UCD3138 Boot ROM supports flash functions. These functions allow the user to perform a mass erase or page erase of either the Program Flash or Data Flash.
Page 445: Boot Rom Mass Erase Data Byte Parameter Values
Like Mass Erase, the Page Erase command requires 20 milliseconds to complete. No PMBus commands should be sent during this time. For the other members of the UCD3138 family, the "flash select" parameter can have different values, depending on which program flash block is being acted upon during the page erase. See Table 13-2 more details.
Page 446: Boot Rom Execute Flash Command Byte, Valid Values
For the other members of the UCD3138 family which have more than one block of program flash, there is sometimes a second option to control which program flash block should be mapped to address 0. For this second option, the command byte should be set to 0xF7.
Page 447: Checksum Functions
13.7 Trim Flash Checksum Verification The Boot ROM also initializes several trim registers in the UCD3138. This trim data comes from a special trim flash area. The trim data is programmed into the trim flash when the device is tested. This trim flash has its own checksum.
Page 448: Ucd3138064 Boot Rom Execution After Power-On/Reset
If program flash block 1 is mapped to address 0x0000, program flash block 2 is mapped to address 0x8000, and vice-versa. The UCD3138 has a PMBus command called “execute flash” with a command code of 0xF0. This causes the program to execute. On the UCD3138064, the same command code causes program flash block 1 to be placed in control.
Page 449: Checksums Used By Ucd3138A64 Boot Rom Program
13.8.2 UCD3138A64 and UCD3138A64A On the UCD3138 and UCD3138064, the checksum for an area of program flash is calculated as the sum of bytes over the program flash area. For example, to calculate the checksum from start_address to end_address, the Boot ROM program on...
Page 450: Ucd3138A64 Boot Rom Execution After Power-On/Reset
Boot ROM for the Other Members of the UCD3138 Family www.ti.com Figure 13-4. UCD3138A64 Boot ROM Execution After Power-on/Reset Figure 13-4 is a flowchart showing the order in which the ROM verifies the integrity of the program flash contents using the different checksums.
Page 451: Ucd3138128 Boot Rom Execution After Power-On/Reset
ROM checksum program from checking the integrity of an empty block of memory. Otherwise a block filled with zeroes would pass the checksum test. The UCD3138 has a PMBus command called “execute flash” with a command code of 0xF0. This causes the program to execute. On the UCD3138128, the same command code cause: •...
Page 452: Arm7Tdmi-S Mpuss
ARM7TDMI-S Modes of Operation ..................14.2 Hardware Interrupts ..................... 14.3 Software Interrupt ................14.4 ARM7TDMI-S Instruction Set ..................14.5 Dual-State Interworking ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 453: Arm Processor Operating Modes
Indicates that the normal register used by User or System mode has been replaced by an alternative register Register specific to the mode of operation. SNIU028A – February 2016 – Revised April 2016 ARM7TDMI-S MPUSS Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 454: Current Program Status Register
It is worth noting that the five Saved Program Status Registers (SPSRs) have the same format as the Current Program Status Register. These registers save the contents of CPSR when an exception occurs. ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 455: Arm Processor Exceptions
FIQ is reserved for one single interrupt source that requires fast response time, like faults or any time critical task that requires fast response Therefore all interrupt sources in UCD3138 peripherals can be mapped into one of the following interrupt service routines.
Page 456: Fast Interrupt (Fiq)
Uint32 arg2, Uint32 arg3, Uint8 swi_number) switch (swi_number) case 0: // Erase one segment of Data Flash return; case 1: return; ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 457: Arm7Tdmi-S Instruction Set
This chapter explains how to set certain sections of code to operate in Thumb (16 bit) or ARM (32 bit) mode. The ARM7TDMI-S (in UCD3138) is a unique processor in that it offers the performance of a 32-bit architecture with the code density of a 16-bit architecture. This is achieved by supporting both a 16-bit instruction set and a 32-bit instruction set and allowing switching dynamically between the two sets.
Page 458: Level Of Dual-State Support
To specify this level of support, use the DUAL_STATE pragma. See section 5.7.2, The DUAL_STATE Pragma, on page 5-15 of TMS470R1x Optimizing C/C++ Compiler User's Guide for more information (SPNU151). ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 459: Implementation
32-BIS state and supports dual-state interworking. Function max( ) is compiled without the −mt option, creating 32-bit instructions. SNIU028A – February 2016 – Revised April 2016 ARM7TDMI-S MPUSS Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 460 LDR A3, [A2, #0] ADD A1, A1, A3 STR A1, [A2, #0] POP {PC} ;***************************************************************** constant table ;***************************************************************** sect ".text" .align4 ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 461: Ucd3138 Reference Code
It is no longer compiled around each function as in 3.3. 14.5.5 UCD3138 Reference Code The UCD3138 reference code provided along with the EVMs (UCD3138PFCEVM-026, UCD3138PSFBEVM-027, UCD3138LLCEVM-028, UCD3138HSFBEVM-029) is written in a way that the program executes mostly in user mode and switches to privileged modes only if it needs to change interrupt configuration or program the flash memory.
Page 462 The “–mt” option can be added by selecting the “16-bit State Code (-mt)” check box under the advanced category. This is illustrated in Figure 14-2. ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 463 These functions are located in the file interrupt.c. Figure 14-3 shows the “file specific” build options for the file interrupts.c which includes the interrupt service routines. SNIU028A – February 2016 – Revised April 2016 ARM7TDMI-S MPUSS Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 464 The manuals above will be for the latest version of CCS. The CCS 3.3 manuals can be accessed via the Help button on the CCS window. They are installed with CCS 3.3. ARM7TDMI-S MPUSS SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 465: Rom And Program Flash Memory Map (Rom Operation)
UCD3138 has programmable memory addressing which is used by the Boot ROM to remap the memories. With the UCD3138, there is no need for the customer to remap memory. However, with the 3138064 and other family members, it may be useful. These chips have more than one program flash block.
Page 466: Memory Map (Flash Operation)
0x0008_0000 - 0x0008_00FF Front End/Ramp I/F 2 Memory Select[10] 0x0009_0000 - 0x0009_00FF Filter 1 Memory Select[11] 0x000A_0000 - 0x000A_00FF DPWM 1 Memory Select[12] Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 467 Note that on 3138 family members with more than one flash block, all the memory select peripherals start at 0x00120000 instead of 0x00020000. SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 468: Static Memory Control Register (Smctrl)
1111 = 15 Wait states ENDIAN Endian Mode Identification 0 = CPU configured in big endian mode 1 = CPU configured in little endian mode Reserved Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 469 Description WIDTH Data Width for Memories 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = Reserved SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 470: Write Control Register (Wctrl)
0 = Write buffer disabled (Disabled) 1 = Write buffer enabled Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 471: Peripheral Control Register (Pctrl)
However, the CPU starts a wait state if there is another request before the memory controller finishes. 0 = Write buffer disabled (Default) 1 = Write buffer enabled SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 472: Peripheral Location Register (Ploc)
These 16 bits represent the peripheral location bits, which correspond to each of the 0000 16 peripheral selects. 0000 0 = Peripheral is internal (Default) 0000 1 = Peripheral is external Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 473: Peripheral Protection Register (Pprot)
Memory Select 15 => DPWM 0 (1Kx32) Memory Select 16 => Front End Control 0 (1Kx32) Memory Select 17 => Program Flash 1(8Kx32) – Not in UCD3138, in all other devices Memory Select 18 => Program Flash 2(8Kx32) - Only in 3138128 Memory Select 19 =>...
Page 474: Memory Fine Base Address High Register 0 (Mfbahr0)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0000 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 475: Memory Fine Base Address Low Register 0 (Mfbalr0)
0 = User/privilege mode accesses to memory (Default) 1 = Privilege mode accesses to memory only SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 476: Memory Fine Base Address High Register 1-3,17-19 (Mfbahrx)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0000 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 477: Memory Fine Base Address Low Register 1-3, 17-19 (Mfbalrx)
0 = User/privilege mode accesses to memory (Default) 1 = Privilege mode accesses to memory only SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 478: Memory Fine Base Address High Load Differences For Enhanced 3138 Devices
15.2.5 Memory Fine Base Address High Load Differences for Enhanced 3138 Devices These tables show the values loaded into the registers in the UCD3138. To make room for additional Program Flash in the UCD3138064 and other devices with more program flash, the registers have an additional bit set that moves the peripherals to start at 0x120000 instead of at 0x20000.
Page 479: Memory Fine Base Address High Register 4 (Mfbahr4)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0010 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 480: Memory Fine Base Address Low Register 4-16 (Mfbalrx)
0 = User/privilege mode accesses to memory (Default) 1 = Privilege mode accesses to memory only Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 481: Memory Fine Base Address High Register 5 (Mfbahr5)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0011 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 482: Memory Fine Base Address High Register 6 (Mfbahr6)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0100 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 483: Memory Fine Base Address High Register 7 (Mfbahr7)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0101 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 484: Memory Fine Base Address High Register 8 (Mfbahr8)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0110 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 485: Memory Fine Base Address High Register 9 (Mfbahr9)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 0111 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 486: Memory Fine Base Address High Register 10 (Mfbahr10)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1000 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 487: Memory Fine Base Address High Register 11 (Mfbahr11)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1001 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 488: Memory Fine Base Address High Register 12 (Mfbahr12)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1010 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 489: Memory Fine Base Address High Register 13 (Mfbahr13)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1011 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 490: Memory Fine Base Address High Register 14 (Mfbahr14)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1100 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 491: Memory Fine Base Address High Register 15 (Mfbahr15)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1101 SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 492: Memory Fine Base Address High Register 16 (Mfbahr16)
16 Most Significant Bits of the Base Address. The Base Address sets the 22 most 0000 significant bits of the memory address. 0000 1110 Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 493: Program Flash Control Register (Pflashctrl)
16.1.8) to initiate Mass Erase cycle. This bit is cleared upon completion of Mass Erase cycle. Reserved PAGE_SEL 00000 Selects page to be erased during Page Erase Cycle SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 494: Data Flash Control Register (Dflashctrl)
1 = Mass Erase of Data Flash enabled. Bit is cleared upon completion of mass erase. Reserved PAGE_SEL 000000 Selects page to be erased during Page Erase Cycle Memory SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 495: Flash Interlock Register (Flashilock)
If the Interlock Key is not set, the write/erase cycle to the Flash will not initiate. This register will clear upon the completion of a write/erase cycle to the Flash modules. SNIU028A – February 2016 – Revised April 2016 Memory Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 496: Control System Module
Memory Management Controller (MMC) ................16.3 System Management (SYS) ................16.4 Central Interrupt Module (CIM) ............16.5 SYS – System Module Registers Reference Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 497: Address Decoder (Dec)
There may be a need for customer programs to erase and program both Program and Data Flash, so this is discussed in some detail. 16.1.1 Memory Mapping Basics There are 4 memory address spaces in the UCD3138. Each memory space has a pair of registers to set its address and block size: Register...
Page 498 0xF000 0x10000 0x11000 0x12000 0x13000 Program 0x14000 FLASH 0x15000 0x16000 0x17000 0x18000 Data FLASH Data FLASH 0x19000 0x1A000 Figure 16-1. Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 499: Base Address
The memory map changes primarily because the vectors – for reset, interrupts, and faults – are located starting at location 0 in memory. When the UCD3138 powers up, the ROM needs to control the vectors. When the memory is configured, but the ROM is still executing, the ROM still needs to control the vectors.
Page 500: Erasing The Programming Flash
Note that all flash operations other than read involve considerable delay. Erase delays, especially, can be several milliseconds. Consult UCD3138 datasheet for specific delay information. 16.1.7 Waiting for Flash Operations to Finish All flash modifications take more than one instruction cycle to complete. Both flash control registers have a BUSY bit that should be checked to verify that no flash process is already underway.
Page 501: Flash Interlock Register
RAM or program Flash. The UCD3138 has 2048 bytes of Data flash organized in 64 blocks of 32 bytes each. Erasing can be done a block at a time. To erase a block, first write the key to the FLASHILOCK register. Then simply write to the Data Flash Control Register (DFLASHCTRL) with the block number in the low 6 bits (PAGE_SEL) and a 1 in bit 9 (PAGE_ERASE).
Page 502: Erasing Program Flash
The request channels are maskable to selectively disable individual channels. Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 503: Interrupt Priority Table
4. IDE, DCM detection DPWM0 DPWM0 same as DPWM1 EXT_FAULT_INT External Faults Fault pin interrupt SYS_SSI_INT System Software System software interrupt 31 (highest) SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 504: Interrupt Handling By Cpu
An interrupt-enable bit to control whether the event occurrence causes an interrupt request to the CIM 16.4.3 CIM Interrupt Management (CIM) A block diagram of the CIM is shown below: Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 505: Cim Input Channel Management
SWI_ALIAS pragma and then calling the software interrupt as if it were a function. A C code example of using software interrupt is shown below: SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 506: Cim Prioritization
DPWM end of period interrupt and two digital fault input pins are all mapped toward the fast interrupt. Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 507 (by hardware) just before the ISR execution ends. Since UCD3138 does not clear the interrupt flags automatically, this should be done by the ISR routine. Negligence to clear the relevant interrupt flag will cause immediate re-invocation of the ISR instantly after previous ISR execution ended.
Page 508: Clock Control Register (Clkcntl)
01 = Driven by the interface clock (ICLK) 10 = Driven by the CPU clock (MCLK) 11 = Driven by the system clock (SYSCLK) Reserved Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 509 0 = CLKOUT driven to logic low in output mode (Default) 1 = CLKOUT driven to logic high in output mode Reserved SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 510: System Exception Control Register (Sysecr)
Illegal Address Reset Override 0 = Illegal address causes a reset or abort (Default) 1 = No action taken on an illegal address Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 511: System Exception Status Register (Sysesr)
1 = Illegal mode has occurred since the last clear User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 512 User and privilege modes (write) 0 = Clears the corresponding bit to 0 1 = No effect Reserved 000 0000 Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 513: Abort Exception Status Register (Abrtesr)
User and privilege modes (write) 0 = Clears bit to 0 1 = No effect 12-0 Reserved 0 0000 0000 0000 SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 514: Global Status Register (Glbstat)
1 = Abort or reset caused by a MPU illegal access User and privilege modes (write) 0 = Clears bit to 0 1 = No effect Reserved 0000 Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 515: Device Identification Register (Dev)
Table 16-9. Device Identification Register (DEV) Register Field Descriptions Field Type Reset Description 15-0 0011 These bits represent the device identification code. 0100 0111 1111 SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 516: System Software Interrupt Flag Register (Ssif)
This bit represents the system software interrupt flag. This bit is set when a correct SSKEY is written to the System Software Interrupt Flag Register. This bit is cleared only by software. Control System Module SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 517: System Software Interrupt Request Register (Ssir)
8-bit field that can be used for passing messages into the system software interrupt. 16.5.9 References 1. UCD3138 Digital Power Peripherals Programmer’s Manual (SLUU995) 2. UCD3138 ARM and Digital System Programmer’s Manual (SLUU994) 3. UCD3138 Device Datasheet (SLUSAP2) SNIU028A – February 2016 – Revised April 2016 Control System Module Submit Documentation Feedback Copyright ©...
Page 518: Flash Memory Programming, Integrity, And Security
This section starts with a quick start summary which gives a recipe for best practices for firmware development and for production. Next, it provides a detailed view of the UCD3138 Flash programming hardware and Boot ROM as a starting point. Finally, it goes into detail with code examples for the exact procedures for Flash management for firmware development and for production.
Page 519: Quick Start Summary
The names just show the main use for each memory. After reset, the UCD3138 starts executing in ROM. In this mode, the ROM is mapped to fill up the entire first 64 Kbytes of memory. The 4 Kbytes of ROM are repeated 16 times.
Page 520: Flash Programming In Rom Mode
It is also possible to write all zeroes to the checksum and clear it. That way, the next time the UCD3138 is reset, it will power up into ROM mode and the memory can be examined. This is best for development, so that the memory contents can be analyzed if necessary.
Page 521: Flash Management For Firmware Development
It is also necessary to ensure that the other chip will not transmit data when the UCD3138 is coming out of reset. If this is done, the UART RX pin can be used as a backdoor, and as an RX pin.
Page 522: Communications Backdoors
The best firmware backdoor is a communications channel based backdoor with a long password, as described above. It could even be a sequence of multiple commands, if desired. Flash Memory Programming, Integrity, and Security SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 523: Firmware Examples
DecRegs.MFBALR1.all = MFBALRX_BYTE0_BLOCK_SIZE_32K + //expand program flash out to 4x real //size MFBALRX_BYTE0_RONLY; while(DecRegs.PFLASHCTRL.bit.BUSY != 0) ; //do nothing while it programs return; SNIU028A – February 2016 – Revised April 2016 Flash Memory Programming, Integrity, and Security Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 524: Erasing Flash
; //do nothing while it programs return; 17.5.3 Serial Port Based Backdoor Here is the code for a back door based on the serial RX line, as used in the UCD3138 training labs: void main() if(GioRegs.FAULTIN.bit.TMS_IN == 0) //emergency backdoor - //TMS is normally pulled up by external resistor clear_integrity_word();...
Page 525: Cim – Central Interrupt Module Registers Reference
FIQ/IRQ Program Control Register (FIRQPR) ..........18.4 Pending Interrupt Read Location Register (INTREQ) ..............18.5 Interrupt Mask Register (REQMASK) SNIU028A – February 2016 – Revised April 2016 CIM – Central Interrupt Module Registers Reference Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 526: Irq Index Offset Vector Register (Irqivec)
2 = Pending interrupt on Channel 1 N = Pending interrupt on Channel N-1, where N <= 31 CIM – Central Interrupt Module Registers Reference SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 527: Fiq Index Offset Vector Register (Fiqivec)
2 = Pending interrupt on Channel 1 N = Pending interrupt on Channel N-1, where N <= 31 SNIU028A – February 2016 – Revised April 2016 CIM – Central Interrupt Module Registers Reference Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 528: Fiq/Irq Program Control Register (Firqpr)
0 = Interrupt request is of IRQ type (Default) 0000 1 = Interrupt request is of FIQ type 0000 0000 0000 CIM – Central Interrupt Module Registers Reference SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 529: Pending Interrupt Read Location Register (Intreq)
31-0 INTREQ Pending Interrupt Requests 0 = No interrupt has occurred 1 = Interrupt is pending SNIU028A – February 2016 – Revised April 2016 CIM – Central Interrupt Module Registers Reference Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 530: Interrupt Mask Register (Reqmask)
0 = Interrupt request channel is disabled (Default) 0000 1 = Interrupt request channel is enabled 0000 0000 0000 0000 0000 CIM – Central Interrupt Module Registers Reference SNIU028A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
Page 531: Revision History
Changes from Original (February 2016) to A Revision ....................Page ................• Global change: removed references to DPWM app note • Updated/Changed document title from "UCD3138 Digital Power Peripherals" to "UCD3138 Digital Power Supply ..........................Controller" ....................• Updated references in Section 2.28 SNIU028A –...
Page 532: Important Notice
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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