Texas Instruments UCD3138 Technical Reference Manual page 512

SYS – System Module Registers Reference
Table 16-6. System Exception Status Register (SYSESR) Register Field Descriptions (continued)
Bit Field
11 ILLADR
10 ILLACC
9 PILLACC
8 ILLMAP
7 SWRST
6-0 Reserved
512
Control System Module
Type Reset
R/W 0
This bit represents the illegal address access flag. This bit is set when an access to
an unimplemented location in the memory map is detected in non-user mode.
User and privilege modes (read)
0 = Illegal address has not occurred since the last clear
1 = Illegal address has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
R/W 0
This bit represents the illegal memory access flag. This bit is set when an access to
a protected location without permission rights is detected in non-user mode.
User and privilege modes (read)
0 = Illegal memory access has not occurred since the last clear
1 = Illegal memory access has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
R/W 0
This bit represents the peripheral illegal access flag. This bit is set when a peripheral
access violation is detected in user mode.
User and privilege modes (read)
0 = Illegal peripheral access has not occurred since the last clear
1 = Illegal peripheral access has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
R/W 0
This bit represents the illegal address map flag. This bit is set when the base
addresses of one or more memories overlap. Reset occurs when the overlapped
registration is accessed.
User and privilege modes (read)
0 = Illegal address mapping has not occurred since the last clear
1 = Illegal address mapping has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
R/W 0
This bit represents the software reset flag. This bit is set when the last reset is
caused by software writing the RESET bits.
User and privilege modes (read)
0 = Software reset has not occurred since the last clear
1 = Software reset has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
R 000 0000
Copyright © 2016, Texas Instruments Incorporated
Description
SNIU028A – February 2016 – Revised April 2016
Submit Documentation Feedback
www.ti.com