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System Overview
2.4.2
Power Sequencing
The processor power-up sequencing is shown in
any other power supply. For our design, VDD_SNVS is powered through a coin cell connected to the CC
pin of the TPS6521815 PMIC, and the DCDC6 supply will always be the first PMIC supply rail to turn on.
Once SNVS voltage is stabilized, then VDD_HIGH_IN should turn on because VDD_HIGH_IN should be
enabled before VDD_SOC_IN for the i.MX 6ULL processor. After VDD_SOC_IN, NVCC_DRAM is turned
on for the DDR3L memory followed by 3.3 V for I/O and analog along with 2.8 V for the LCD screen. The
final supply to turn on is the 1.8-V I/O rail. Once all these voltages are enabled and within regulation, there
is a delay before PGOOD is set high. PGOOD is the PMIC output that control the power-on reset
(POR_B) input of the processor.
The processor power-down sequencing is shown in
sequence.
Figure 16. Required Power-Up Sequence for i.MX 6ULL Processor
Figure 17. Required Power-Down Sequence for i.MX 6ULL Processor
NVCC_XXX, VDDA_ADC_3P3,
18
Integrated Power Supply Reference Design for NXP i.MX 6ULL
VDD_SNVS_IN
(3 V, coin cell/DCDC6)
VDD_HIGH_IN
(3.3 V, DCDC3)
VDD_SOC_IN
(1.325 V/1.27 V, DCDC1)
NVCC_DRAM
(1.35 V, DCDC2)
NVCC_XXX, VDDA_ADC_3P3,
VDD_PERI_3V3 (3.3 V), VDD_2V8
(LS1, LDO1, 3V3 switch)
NVCC_NAND
(1.8 V, DCDC4)
USB_OTG_VBUS 1& 2
(5 V, LS2, LS3, LS4)
POR_B
(PGOOD)
POR_B
(PGOOD)
USB_OTGx_VBUS
(5 V, LS2, LS3 & LS4)
T1>=0
NVCC_NAND
(1.8 V, DCDC4)
VDD_PERI_3V3, VDD_2V8
(LS1, LDO1, 3V3 switch)
NVCC_DRAM
(1.35 V, DCDC2)
VDD_SOC_IN
(1.325/1.27 V, DCDC1)
VDD_HIGH_IN
(3.3 V , DCDC3)
VDD_SNVS_IN
(3 V, coin cell/DCDC6)
Copyright © 2020, Texas Instruments Incorporated
Figure
16. First the VDD_SNVS needs to turn on before
Figure
17, which is the reverse of the power-up
t1>0
t2>0
t3>0
t4>=0
t5>=0
t6>0
T2>=0
T3>0
T4>0
T5>0
T6>0
www.ti.com
t7>0
T7>0
TIDUEW7 – May 2020
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