Outline Of Reset - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 4 RESET
4.1

Outline of Reset

When the reset cause is generated, the CPU suspends the currently executed process
immediately before entering the wait state for release of the reset. After the reset is
cleared, processing starts from the address indicated in the reset vector.
There are the following four kinds of factors of resets.
• Generation power on reset
• Watchdog timer overflow
• Generation of external reset request from RST terminal
• Generation of software reset request
Reset Factor
Table 4.1-1 shows the causes of reset.
Table 4.1-1 Reset Factor
Reset
Power on At power on
Watchdog timer Watchdog timer overflow
External pin Input "L" level to RST pin
A "0" is written to the RST bit
of low-power consumption
Software
mode control register
(LPMCR)
Main clock: Oscillation clock frequency divided by 2
Power on reset
Power on reset is reset generated at power on. For an evaluation or flash product, the oscillation
stabilization wait time is 2
product, this wait time is 2
starts after elapsing the oscillation stabilization wait time.
Watchdog reset
Watchdog reset generates a reset in response to an overflow of the watchdog timer after start of the
watchdog timer. This overflow occurs when a "0" is not written in the watchdog control bit (WTE) of the
watchdog timer control register (WDTC) within the predetermined time. The oscillation stabilization wait
time can be selected using the clock select register (CKSCR).
114
Generation factor
18
/HCLK (approx. 43.70 ms at an oscillation clock of 6 MHz). For a MASK
17
/HCLK (approx. 21.85 ms at an oscillation clock of 6 MHz). Reset operation
Machine clock Watchdog timers
Main clock
(MCLK)
Main clock
(MCLK)
Main clock
(MCLK)
Main clock
(MCLK)
Oscillation
stability waiting
Stops Yes
Stops None
Stops None
Stops None