Fujitsu F2MC-16LX Hardware Manual page 115

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Note:
If writing transmission data to UART by using µDMAC, not setting RDY2 and RDY1 bit of DMACS
register in (0, 0).
Figure 3.8-10 Wait Specification Bit Explanation
destination wait
Length of wait part in transfer such as above
figure is defined by RDY2 and RDY1.
CHAPTER 3 INTERRUPT
source destination
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