Fujitsu F2MC-16LX Hardware Manual page 230

CHAPTER 9 TIMEBASE TIMER
Table 9.5-1 Timebase Timer Counter Clearance Operation and Oscillation Stabilization Wait Time
Operation
Writing "0" to timebase timer
initialization bit (TBR) of timebase
timer control register (TBTC)
Power-on reset
Watchdog reset
Release of main stop mode
Release of PLL stop mode
Release of Sub-stop mode
Transition from main clock mode to
PLL clock mode (MCS=1 → 0)
Transition from sub-clock mode to
main clock mode (MCS=1 → 1)
Release of timebase timer mode
Release of sleep mode
: Yes
: None
Function of Clock Supply
The timebase timer supplies clock to the watchdog timer. The clearance of timebase counter effects the
operation of watchdog timer.
214
Counter TBOF
Clear
Oscillation Stabilization Wait Time
Main clock oscillation stabilization wait time
Sub-clock oscillation stabilization wait time
PLL clock oscillation stabilization wait time
Main clock oscillation stabilization wait time