Fujitsu F2MC-16LX Hardware Manual page 227

Table 9.3-1 Timebase Timer Control Register (TBTC)
Bit name
Reserved:
bit 15
Reserved bit
bit 14
Unused bits
bit 13
TBIE:
bit 12 Interrupt request
enable bit
TBOF:
bit 11 Interrupt request
flag bit
TBR:
bit 10 Timebase timer
initialization bit
TBC1, TBC0:
bit 9
Interval time
bit 8
select bits
Note:
Be sure to write "1".
• The value at the time of reading is irregular.
• No effect on writing.
• This bit permits or prohibits an interrupt request output to the CPU.
• If the TBIE bit and interrupt request flag bit (TBOF) is set to "1", an interrupt request is
output.
• An overflow of timebase timer counter specification bit sets the status to "1".
• If the TBOF bit and interrupt request permission bit (TBIE) is set to "1", an interrupt request
is output.
Setting to "0" executes clearance during writing and no changes are made at "1", making no
influences on others.
Note:
• When clearing the TBOF bit, set to the condition that prohibits timebase timer interrupt with
the interrupt request permission bit (TBIE) or by specifying interrupt level mask register
(ILM) in processor status (PS).
• The status is cleared to "0" by "0" writing, transition to the stop mode, transition from the
sub clock mode to main clock mode, transition from the main clock mode to the PLL clock
mode, "0" writing to timebase timer initialization bit (TBR), or resetting.
• This bit clears the timebase timer counter.
• Writing "0" clears the counter, immediately after that, clears the TBOF bit. No changes are
made at "1", making no influences on others.
Reference:
Always read value is "1".
• These bits specify a cycle for the interval timer.
• The bit for the interval timer of timebase timer counter is specified.
• One of four interval time can be selected.
CHAPTER 9 TIMEBASE TIMER
Functions
211