Fujitsu F2MC-16LX Hardware Manual page 146

16-bit microcontroller mb90330 series

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Table of Contents

CHAPTER 5 CLOCK

Reset (Cancellation)

Interrupt (Cancellation)

System clock generation circuit

Generates an oscillation clock (HCLK) using the oscillator connected to the high-speed oscillation pin. It is

also possible to input an external clock.

Sub clock generator circuit

Generates the sub clock (SCLK) using the oscillator connected to the low-speed oscillation pin. It is also

possible to input an external clock.

Figure 5.2-1 Block Diagram of Clock Generation Section

Low power consumption mode control register (LPMCR)

PLL frequency

multiplication circuit

Clock selection register (CKSCR)

Oscillation clock

Oscillation clock

generation circuit

System clock

generation circuit

CPU intermittent

operation sector

control circuit

Timebase timer

control circuit

Internal reset

Intermittent cycle

control circuit

Watch, Stop, Sleep signal

Watch, Stop signal

Oscillation stable

wait cancellation

control circuit

Sub clock oscillation stabilization wait cancellation

Main clock oscillation stabilization wait cancellation

to Watchdog timer