Stop Mode - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.4

Stop Mode

Stop mode is mode for stopping original oscillation and all functions are stopped. That
means, data can be held with the lowest power consumption.
Transition to Stop Mode
If you write "1" into the stop mode bit (STP) of the low-power consumption mode control register
(LPMCR), the transition to the stop mode is made.
Data retention function
In the stop mode, the contents of the dedicated registers such as accumulators and the internal RAM are
held unchanged.
Holding function
In the stop mode, the external bus hold function is terminated, thereby neglecting a hold request even a
request is input. If you input a hold request while transiting to the stop mode, the HAK signal may not get
to "L" with the bus being high impedance.
Operation during an interrupt request
When you write "1" into the SLP bit of the LPMCR register, the transition to the stop mode is not made if
there is an interrupt request.
Pin state setting
You may determine by the pin state specification bit (SPL) of the LPMCR register whether the external pin
in the stop mode should be retained in the preceding state or be shifted into the high impedance state.
Cancellation of Stop Modes
The low-power consumption control circuit clears stop mode when reset input or interrupt occurs. As
oscillation of the operation clock is stopped when returning from stop mode, the low-power consumption
control circuit first transits to the oscillation stabilization wait state and then clears stop mode.
Return by Reset
When clearing stop mode by a reset cause, transition occurs to oscillation stabilization wait reset state after
clearing stop mode. The reset sequence is executed after the oscillation stabilization wait time.
Return by interrupt
If there is an interrupt request higher than level 7 from the peripheral circuit and others in the stop mode
(except for IL2, IL1, IL0 of the interrupt control register (ICR) = "111
control circuit cancels the stop mode. After canceling the stop mode, a normal interrupt procedure is
executed when elapsing the main clock oscillation stable wait time specified by the oscillation stable wait
time selection bit (WS1, WS0) of the clock selection register (CKSCR). When an interrupt is acceptable by
settings in the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the
interrupt control register (ICR), interrupt processing is carried out. When an interrupt is not acceptable,
processing from the instruction succeeding the one caused to enter stop mode continues.
158
"), the low-power consumption
B