Fujitsu F2MC-16LX Hardware Manual page 451

Table 19.3-1 Description and Functions of Each Bit of A/D Control Status Register (High) (ADCS1)
Bit name
bit15 BUSY:
Under the
conversion bit
bit14 INT:
Interrupt
request flag
bit
bit13 INTE:
Interrupt
demand
permission bit
bit12 PAUS:
Temporary
stop flag bit
bit11 STS1, STS0:
bit10 A/D startup
factor
selection bits
bit9 STRT:
Analog to
digitalizing
A/D converter
start up bit
bit8 Reserved:
reserved bit
• The operation display bit of A/D converter.
• When the BUSY bit is "0" and "1" in the read process, it indicates the stopped A/D conversion
and the operated A/D conversion, respectively.
• When "0" is written in the BUSY bit in the write process, the A/D conversion operation is
forcibly stopped. When "1" is written, the conversion is not changed and no others are
affected.
Note:
Do not perform the forced stop and the software start (BUSY = 0, STRT = 1) at the same
time.
• When the data are set to the A/D data register by the A/D conversion, the INT bit is set to "1".
• When the INT bit and the interrupt request enabled bit (ADCS1: INTE) are set to "1", the
interrupt request is generated. If EI
• When "0" is set in the write process, the INT bit is cleared. When "1" is set, it is not changed
and no others are affected.
• The INT bit is cleared by the startup of EI
Note:
The A/D must be stopped when writing "0" in the INT bit for clearing.
• This bit is used to enable and disable the interrupt output to CPU.
• When the INTE bit and the interrupt request flag bit (ADCS1: INT) are set to "1", the interrupt
request is generated.
• Set it to "1" when using the EI
• It is set to "1" when the A/D conversion operation is suspended.
• Since this A/D converter has only one A/D data register, when the CPU has not yet completed
to read the old conversion result by using the continuous conversion mode, the old conversion
data are lost by a new conversion result. Therefore, to use the continuous conversion mode, the
automatic transfer of conversion result to the memory must be basically set by using the EI
at every conversion termination. However, such case can be assumed that the conversion data
transfer is not completed before the next conversion in the multiple interrupts, etc. The PAUS
bit is the function to prepare for the such case. When the PAUS bit is set to "1", the A/D
conversion is stopped so that the next conversion data are not stored during the period from the
conversion termination to the data register contents transfer with the EI
D converter automatically restarts the conversion at the transfer termination with the EI
Note:
2
Only when EI OS is used, the PAUS bit is effective.
• The start factor of A/D conversion is selected.
• When the start factor is in the common use, the first start factor generation starts the operation.
Note:
Switch the start factor when the target start factor is not present to update it during the A/D
conversion operation because it is changed at the same time of updating.
• This bit is used to start the A/D conversion operation by the software.
• When "1" is written in the STRT bit, the A/D conversion is started.
• During the suspend conversion mode, the restart operation by STRT bit is not performed.
Note:
Forcibly stop and software start up must not be done at the same time.
Note:
Be sure to write "0".
CHAPTER 19 8/10-BIT A/D CONVERTER
Functions
2
OS has been permitted, EI
2
OS.
2
OS.
2
OS is started.
2
OS. After that, the A/
2
OS.
2
OS
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