Fujitsu F2MC-16LX Hardware Manual page 66

CHAPTER 3 INTERRUPT
Interruption by µDMAC
µDMAC is involved in automatic data transfer between peripheral functions and memory. EI
data transfer by DMA transfer although it was previously performed by the interrupt handling program.
Once the data transfer process has been performed the specified number of times, µDMAC automatically
executes the interrupt handling program.
Interruption by µDMAC is a type of hardware interrupt.
Memory space
I/O register
Buffer
DCT
IOA: I/O address pointer
BAP: Buffer address pointer
(1)
The peripheral resource (I/O) requests DMA transfer.
(2)
When the corresponding bit of DMA enable register (DER) is "1", DMAC reads from the descriptor the transfer data
such as the transfer source address, transfer destination address, and transfer count of specified channels.
(3)
DMA data transfer is started between I/O and memory.
(4)
After one item (either Byte data or Word data) transferred.
(a)
Transfer has not been completed (DCT does not reached to 0):
µDMAC requests to clear the DMA transfer request to the peripheral resouece.
(b)
At transfer end (DCT reached to 0):
After completion of DMA transfer, the flag indicating completion of transfer is set in the DMA status register,
outputting an interrupt request to the interrupt controller.
Note: Write access to the internal registers DCSR, DSRH, DSRL, DSSR, DERH, and DERL is prohibited during DMA transfer.
Exception processing
Exception processing, basically the same as interrupt, is executed when an exception item (execution of an
undefined instruction) is detected at an instruction-to-instruction boundary; the normal process is
suspended for this purpose. Equivalent to software interrupt instruction "INT10".
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Figure 3.1-4 Overview of the Direct Memory access (DMA)
IOA
I/O register
(4) (a)
(3) DMA controller
BAP
CPU
DER: DMA enable register
DCT: Data counter
Peripheral
function
(I/O)
(1)
(2)
(2)
(4) (b)
Interrupt
controller
2
OS performs
RAM for
descriptor
DMA
descriptor