Check The Execution State Of Automatic Algorithm - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 25 3M-BIT FLASH MEMORY
25.5

Check the Execution State of Automatic Algorithm

Because write/erase flow are performed through automatic algorithm in flash memory,
the algorithm must wait signals from hardware that notify the operation conditions or
operation end. This automatic algorithm can check the operation state of the internal
flash memory by the following hardware sequence.
Hardware Sequence Flag
The hardware sequence flag consists of 5-bit outputs: DQ7, DQ6, DQ5, DQ3, and DQ2. Each bit has the
functions of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit excess flag (DQ5), sector erase
timer flag (DQ3), and toggle bit 2 flag (DQ2). These flags can be used to confirm whether write/chip sector
erase end and erase code write are effective or not.
Reference to the hardware sequence flag, read-access to the address in the target sector in the flash memory
after setting the command sequence (See Table 25.4-1). Table 25.5-1 shows the bit allocation of the
hardware sequence flag.
Table 25.5-1 Bit Allocation of Hardware Sequence Flag
Hardware sequence flag
To check if the automatic write/chip sector erase is operating or ended, verify the hardware sequence flag
or the RDY bit of the flash memory control register (FMCS). After the write/erase commands end, it
returns to the read/reset state. When actually creating a program, perform the following procedures
including data read after verifying the automatic write/erase end with one of these flags. Also, you can
check if the sector erase code write after the second command is enabled by using the hardware sequence
flag. The next section describes each hardware sequence flag.
Table 25.5-2 shows the list of the hardware sequence flag functions.
570
Bit No. 7
DQ7
6 5 4
DQ6 DQ5 -
3 2 1
DQ3 DQ2 -
0
-